> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Monk Liu > Sent: Thursday, May 04, 2017 6:05 AM > To: [email protected] > Cc: Liu, Monk > Subject: [PATCH 3/6] drm/amdgpu:change SR-IOV DMAframe scheme > > According to CP/hw team requirment, to support PAL/CHAINED-IB > MCBP, kernel driver must guarantee DE_META must be inserted > right prior to the work_load DE IB (with PREEMPT flag), there > cannot be any non-work_load DE IB between-in DE_META and > work_load DE IB. > > Change-Id: Ie060f1a39effa1edd5e3bf10c08624ffc82dfa44 > Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 9 +++++---- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++---- > 2 files changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index e547df4..eed5745 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -6407,9 +6407,13 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct > amdgpu_ring *ring, > > control |= ib->length_dw | (vm_id << 24); > > - if (amdgpu_sriov_vf(ring->adev) && ib->flags & > AMDGPU_IB_FLAG_PREEMPT) > + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & > AMDGPU_IB_FLAG_PREEMPT)) { > control |= INDIRECT_BUFFER_PRE_ENB(1); > > + if (!(ib->flags & AMDGPU_IB_FLAG_CE)) > + gfx_v8_0_ring_emit_de_meta(ring); > + } > + > amdgpu_ring_write(ring, header); > amdgpu_ring_write(ring, > #ifdef __BIG_ENDIAN > @@ -6618,9 +6622,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct > amdgpu_ring *ring, uint32_t flags) > amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, > 1)); > amdgpu_ring_write(ring, dw2); > amdgpu_ring_write(ring, 0); > - > - if (amdgpu_sriov_vf(ring->adev)) > - gfx_v8_0_ring_emit_de_meta(ring); > } > > static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring > *ring) > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 6857581..f192297 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -119,6 +119,7 @@ static int gfx_v9_0_get_cu_info(struct > amdgpu_device *adev, > struct amdgpu_cu_info *cu_info); > static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device > *adev); > static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 > se_num, u32 sh_num, u32 instance); > +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); > > static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) > { > @@ -2882,9 +2883,13 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct > amdgpu_ring *ring, > > control |= ib->length_dw | (vm_id << 24); > > - if (amdgpu_sriov_vf(ring->adev) && (ib->flags & > AMDGPU_IB_FLAG_PREEMPT)) > + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & > AMDGPU_IB_FLAG_PREEMPT)) { > control |= INDIRECT_BUFFER_PRE_ENB(1); > > + if (!(ib->flags & AMDGPU_IB_FLAG_CE)) > + gfx_v9_0_ring_emit_de_meta(ring); > + } > + > amdgpu_ring_write(ring, header); > BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ > amdgpu_ring_write(ring, > @@ -3124,9 +3129,6 @@ static void gfx_v9_ring_emit_cntxcntl(struct > amdgpu_ring *ring, uint32_t flags) > amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, > 1)); > amdgpu_ring_write(ring, dw2); > amdgpu_ring_write(ring, 0); > - > - if (amdgpu_sriov_vf(ring->adev)) > - gfx_v9_0_ring_emit_de_meta(ring); > } > > static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring > *ring) > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
