From 109b8cbf83c704e881ae92261fe556fb71a5bffd Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Tue, 9 May 2017 12:04:24 -0400 Subject: [PATCH 1/4] drm/amdgpu: Add vm context module param Add VM context module param (amdgpu.vm_update_context) that can used to control how the VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU However, CPU based update is only supported for large BAR systems. By default, vm_update_context = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU (for large BAR system). Change-Id: I95b2913b30d1027d1224a97e0ec92c08ae6494f2 Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 17 ++++++++++++++++- 5 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5310781..d420ae5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -93,6 +93,7 @@ extern int amdgpu_vm_block_size; extern int amdgpu_vm_fault_stop; extern int amdgpu_vm_debug; +extern int amdgpu_vm_update_context; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 416908a..5b8a6ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -93,6 +93,7 @@ int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; +int amdgpu_vm_update_context = 2; int amdgpu_vram_page_split = 1024; int amdgpu_exp_hw_support = 0; int amdgpu_dc = -1; @@ -179,6 +180,9 @@ MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); +MODULE_PARM_DESC(vm_update_context, "VM update using CPU on large BAR. (0 = never, 1 = Graphics only, 2 = Compute only (default), 3 = Both"); +module_param_named(vm_update_context, amdgpu_vm_update_context, int, 0444); + MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index c2d4465..e2b394e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -757,7 +757,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto out_suspend; } - r = amdgpu_vm_init(adev, &fpriv->vm); + r = amdgpu_vm_init(adev, &fpriv->vm, + !!(amdgpu_vm_update_context & + AMDGPU_VM_USE_CPU_UPDATE_FOR_GRAPHICS_MASK)); if (r) { kfree(fpriv); goto out_suspend; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ed97a2e..b5871f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -694,6 +694,13 @@ static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) return addr; } +static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) +{ + if (adev->mc.visible_vram_size > 0 && + adev->mc.real_vram_size == adev->mc.visible_vram_size) + return true; + return false; +} /** * amdgpu_vm_flush - hardware flush the vm * @@ -2234,10 +2241,12 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) * * @adev: amdgpu_device pointer * @vm: requested vm + * @vm_update_mode: FALSE use SDMA, TRUE use CPU to update page tables * * Init @vm fields. */ -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm + bool vm_update_mode) { const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT(adev) * 8); @@ -2265,7 +2274,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) rq, amdgpu_sched_jobs); if (r) return r; - + /* CPU update is only supported for large BAR system */ + vm->is_vm_update_mode_cpu = (vm_update_mode && + amdgpu_vm_is_large_bar(adev)); + DRM_DEBUG_DRIVER("VM update mode is %s\n", + vm->is_vm_update_mode_cpu ? "CPU" : "SDMA"); vm->last_dir_update = NULL; r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index abc0bab..46fde0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -96,6 +96,17 @@ struct amdgpu_vm_pt { unsigned last_entry_used; }; +/* amdgpu_vm_update_context - User parameter that controls how VM pde/pte are + * updated for Graphics and Compute. BIT0 controls Graphics and BIT1 controls + * Compute. + * BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU + * BIT1 [= 0] Compute updated by SDMA [= 1] by CPU + * NOTE: CPU update is supported only in large BAR systems + */ +#define AMDGPU_VM_USE_CPU_UPDATE_FOR_GRAPHICS_MASK (1 << 0) +#define AMDGPU_VM_USE_CPU_UPDATE_FOR_COMPUTE_MASK (1 << 1) + + struct amdgpu_vm { /* tree of virtual addresses mapped */ struct rb_root va; @@ -129,6 +140,9 @@ struct amdgpu_vm { struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; /* each VM will map on CSA */ struct amdgpu_bo_va *csa_bo_va; + + /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ + bool is_vm_update_mode_cpu : 1; }; struct amdgpu_vm_id { @@ -190,7 +204,8 @@ struct amdgpu_vm_manager { void amdgpu_vm_manager_init(struct amdgpu_device *adev); void amdgpu_vm_manager_fini(struct amdgpu_device *adev); -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + bool vm_update_mode); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, -- 1.9.1