Fix indentation and use WREG32_FIELD to clean up.

Signed-off-by: Tom St Denis <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index eccf4c467fe1..cd793c262674 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -302,13 +302,9 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
 
        /* enable UMC */
        WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
-
-       WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
-
-       WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
-
-       WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-
+       WREG32_FIELD(UVD_SOFT_RESET, LMI_SOFT_RESET, 0);
+       WREG32_FIELD(UVD_SOFT_RESET, LMI_UMC_SOFT_RESET, 0);
+       WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
        mdelay(10);
 
        for (i = 0; i < 10; ++i) {
@@ -324,10 +320,9 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
                        break;
 
                DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
-               WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
-                               ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+               WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
                mdelay(10);
-               WREG32_P(mmUVD_SOFT_RESET, 0, 
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+               WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
                mdelay(10);
                r = -1;
        }
@@ -339,7 +334,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
 
        /* enable interupt */
        WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
-
        WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
 
        /* force RBC into idle state */
@@ -348,7 +342,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
        /* Set the write pointer delay */
        WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 
-       /* programm the 4GB memory segment for rptr and ring buffer */
+       /* program the 4GB memory segment for rptr and ring buffer */
        WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
                                   (0x7 << 16) | (0x1 << 31));
 
@@ -420,7 +414,6 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
        }
 
        WREG32_P(0x3D49, 0, ~(1 << 2));
-
        WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
 
        /* put LMI, VCPU, RBC etc... into reset */
-- 
2.12.0

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