> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Rex Zhu > Sent: Wednesday, May 31, 2017 8:16 AM > To: [email protected] > Cc: Zhu, Rex > Subject: [PATCH 2/4] drm/amd/powerplay: Add floor DCEF for DS on boot. > > Change-Id: I2385a3695ce28139e51088d2eacae299aaf476aa > Signed-off-by: Rex Zhu <[email protected]>
Please include a better patch description. Something like: "Use the vbios to look up the default frequencies for socclk and dcefclk." With that fixed: Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 31 > +++++++++++++++++++++- > drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 3 +++ > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 +++ > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 + > 4 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c > index 5602311..1ba05cc 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c > @@ -388,11 +388,33 @@ int pp_atomfwctrl_get_gpio_information(struct > pp_hwmgr *hwmgr, > return 0; > } > > +int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr > *hwmgr, BIOS_CLKID id, uint32_t *frequency) > +{ > + struct atom_get_smu_clock_info_parameters_v3_1 parameters; > + struct atom_get_smu_clock_info_output_parameters_v3_1 > *output; > + uint32_t ix; > + > + parameters.clk_id = id; > + parameters.command = > GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; > + > + ix = GetIndexIntoMasterCmdTable(getsmuclockinfo); > + if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, ¶meters)) { > + output = (struct > atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters; > + *frequency = output- > >atom_smu_outputclkfreq.smu_clock_freq_hz / 10000; > + } else { > + pr_info("Error execute_table getsmuclockinfo!"); > + return -1; > + } > + > + return 0; > +} > + > int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, > struct pp_atomfwctrl_bios_boot_up_values > *boot_values) > { > struct atom_firmware_info_v3_1 *info = NULL; > uint16_t ix; > + uint32_t frequency = 0; > > ix = GetIndexIntoMasterDataTable(firmwareinfo); > info = (struct atom_firmware_info_v3_1 *) > @@ -407,11 +429,18 @@ int > pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, > boot_values->ulRevision = info->firmware_revision; > boot_values->ulGfxClk = info->bootup_sclk_in10khz; > boot_values->ulUClk = info->bootup_mclk_in10khz; > - boot_values->ulSocClk = 0; > boot_values->usVddc = info->bootup_vddc_mv; > boot_values->usVddci = info->bootup_vddci_mv; > boot_values->usMvddc = info->bootup_mvddc_mv; > boot_values->usVddGfx = info->bootup_vddgfx_mv; > + boot_values->ulSocClk = 0; > + boot_values->ulDCEFClk = 0; > + > + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, > SMU9_SYSPLL0_SOCCLK_ID, &frequency)) > + boot_values->ulSocClk = frequency; > + > + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, > SMU9_SYSPLL0_DCEFCLK_ID, &frequency)) > + boot_values->ulDCEFClk = frequency; > > return 0; > } > \ No newline at end of file > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h > index 43a6711..81908b5 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h > @@ -26,6 +26,8 @@ > > #include "hwmgr.h" > > +typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; > + > #define GetIndexIntoMasterCmdTable(FieldName) \ > (((char*)(&((struct > atom_master_list_of_command_functions_v2_1*)0)->FieldName)- > (char*)0)/sizeof(uint16_t)) > #define GetIndexIntoMasterDataTable(FieldName) \ > @@ -125,6 +127,7 @@ struct pp_atomfwctrl_bios_boot_up_values { > uint32_t ulGfxClk; > uint32_t ulUClk; > uint32_t ulSocClk; > + uint32_t ulDCEFClk; > uint16_t usVddc; > uint16_t usVddci; > uint16_t usMvddc; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index a50a6ef..30bc053 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -2451,6 +2451,7 @@ static int vega10_init_smc_table(struct pp_hwmgr > *hwmgr) > data->vbios_boot_state.gfx_clock = > boot_up_values.ulGfxClk; > data->vbios_boot_state.mem_clock = > boot_up_values.ulUClk; > data->vbios_boot_state.soc_clock = > boot_up_values.ulSocClk; > + data->vbios_boot_state.dcef_clock = > boot_up_values.ulDCEFClk; > if (0 != boot_up_values.usVddc) { > smum_send_msg_to_smc_with_parameter(hwmgr- > >smumgr, > > PPSMC_MSG_SetFloorSocVoltage, > @@ -2459,6 +2460,9 @@ static int vega10_init_smc_table(struct pp_hwmgr > *hwmgr) > } else { > data->vbios_boot_state.bsoc_vddc_lock = false; > } > + smum_send_msg_to_smc_with_parameter(hwmgr- > >smumgr, > + PPSMC_MSG_SetMinDeepSleepDcefclk, > + (uint32_t)(data->vbios_boot_state.dcef_clock / > 100)); > } > > result = vega10_populate_avfs_parameters(hwmgr); > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > index 1d7dbad..6e5c5b9 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > @@ -185,6 +185,7 @@ struct vega10_vbios_boot_state { > uint32_t gfx_clock; > uint32_t mem_clock; > uint32_t soc_clock; > + uint32_t dcef_clock; > }; > > #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
