From: Nicolai Hähnle <nicolai.haeh...@amd.com>

This is ported from gfx8.

Signed-off-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5d56126..166138b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4409,51 +4409,71 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device 
*adev)
                adev->gds.mem.cs_partition_size = 1024;
 
                adev->gds.gws.gfx_partition_size = 16;
                adev->gds.gws.cs_partition_size = 16;
 
                adev->gds.oa.gfx_partition_size = 4;
                adev->gds.oa.cs_partition_size = 4;
        }
 }
 
+static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
+                                                u32 bitmap)
+{
+       u32 data;
+
+       if (!bitmap)
+               return;
+
+       data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
+       data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
+
+       WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
+}
+
 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
 {
        u32 data, mask;
 
        data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
        data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
 
        data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
        data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
 
        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
 
        return (~data) & mask;
 }
 
 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                                 struct amdgpu_cu_info *cu_info)
 {
        int i, j, k, counter, active_cu_number = 0;
        u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
+       unsigned disable_masks[4 * 2];
 
        if (!adev || !cu_info)
                return -EINVAL;
 
+       amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
                        mask = 1;
                        ao_bitmap = 0;
                        counter = 0;
                        gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+                       if (i < 4 && j < 2)
+                               gfx_v9_0_set_user_cu_inactive_bitmap(
+                                       adev, disable_masks[i * 2 + j]);
                        bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
                        cu_info->bitmap[i][j] = bitmap;
 
                        for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
                                if (bitmap & mask) {
                                        if (counter < 
adev->gfx.config.max_cu_per_sh)
                                                ao_bitmap |= mask;
                                        counter ++;
                                }
                                mask <<= 1;
-- 
2.9.3

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