SMN address is larger than 32 bits for registers on different AID's Updating existing interface to support access to such registers.
Signed-off-by: Mangesh Gadre <[email protected]> Reviewed-by: Christian König <[email protected]> --- v2 : Adding hardware family check for creating debugfs interface for PCIe register access v3 : Instead of creating new debugfs interface,now using existing interface with address range check for call to appropriate interface (Lijo) v4 : Using available helper instead of explicit right shift operations (Christian) drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 96d634bfa448..391af8060704 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -559,7 +559,11 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, while (size) { uint32_t value; - value = RREG32_PCIE(*pos); + if (upper_32_bits(*pos)) + value = RREG32_PCIE_EXT(*pos); + else + value = RREG32_PCIE(*pos); + r = put_user(value, (uint32_t *)buf); if (r) goto out; @@ -619,7 +623,10 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user if (r) goto out; - WREG32_PCIE(*pos, value); + if (upper_32_bits(*pos)) + WREG32_PCIE_EXT(*pos, value); + else + WREG32_PCIE(*pos, value); result += 4; buf += 4; -- 2.34.1
