On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling <[email protected]> wrote: > From: shaoyunl <[email protected]> > > For GFX context, the ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS can be cleared > to perform in VM mode. For RLC context, to support ATC mode , ATC bit in > SDMA*_RLC*_VIRTUAL_ADDRESS should be set. SDMA_CNTL.ATC_L1_ENABLE bit is > global setting that enables the L1-L2 translation for ATC address. > > Signed-off-by: shaoyun liu <[email protected]> > Reviewed-by: Felix Kuehling <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index 1d766ae..67a29fb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -556,12 +556,18 @@ static void sdma_v3_0_ctx_switch_enable(struct > amdgpu_device *adev, bool enable) > > for (i = 0; i < adev->sdma.num_instances; i++) { > f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); > - if (enable) > + if (enable) { > f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > AUTO_CTXSW_ENABLE, 1); > - else > + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > + ATC_L1_ENABLE, 1); > + } else { > f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > AUTO_CTXSW_ENABLE, 0); > + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > + ATC_L1_ENABLE, 1); > + } > + > WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); > } > } > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
