> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Nicolai Hähnle > Sent: Friday, July 14, 2017 7:42 AM > To: [email protected] > Cc: Haehnle, Nicolai > Subject: [PATCH] drm/amdgpu/gfx9: simplify and fix GRBM index selection > > From: Nicolai Hähnle <[email protected]> > > Copy the approach taken by gfx8, which simplifies the code, and set the > instance index properly. The latter is required for debugging, e.g. for > reading wave status by UMR. > > Signed-off-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 6986285..020da95 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1468,35 +1468,37 @@ static int gfx_v9_0_sw_fini(void *handle) > } > > > static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) > { > /* TODO */ > } > > static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 > se_num, u32 sh_num, u32 instance) > { > - u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, > INSTANCE_BROADCAST_WRITES, 1); > + u32 data; > > - if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { > - data = REG_SET_FIELD(data, GRBM_GFX_INDEX, > SH_BROADCAST_WRITES, 1); > - data = REG_SET_FIELD(data, GRBM_GFX_INDEX, > SE_BROADCAST_WRITES, 1); > - } else if (se_num == 0xffffffff) { > - data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, > sh_num); > + if (instance == 0xffffffff) > + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, > INSTANCE_BROADCAST_WRITES, 1); > + else > + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, > INSTANCE_INDEX, instance); > + > + if (se_num == 0xffffffff) > data = REG_SET_FIELD(data, GRBM_GFX_INDEX, > SE_BROADCAST_WRITES, 1); > - } else if (sh_num == 0xffffffff) { > - data = REG_SET_FIELD(data, GRBM_GFX_INDEX, > SH_BROADCAST_WRITES, 1); > + else > data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, > se_num); > - } else { > + > + if (sh_num == 0xffffffff) > + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, > SH_BROADCAST_WRITES, 1); > + else > data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, > sh_num); > - data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, > se_num); > - } > + > WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); > } > > static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) > { > u32 data, mask; > > data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); > data |= RREG32_SOC15(GC, 0, > mmGC_USER_RB_BACKEND_DISABLE); > > -- > 2.9.3 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
