On Thu, Jul 20, 2017 at 11:26:37AM +0800, Hawking Zhang wrote: > Change-Id: I32d98b77b8da6b180dd365ff7f99c08e8aa061b1 > Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Huang Rui <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- > drivers/gpu/drm/amd/amdgpu/gchub_v9_0.c | 343 > +++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/gchub_v9_0.h | 36 ++++ > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 343 > ------------------------------- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 36 ---- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +- > drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- > 10 files changed, 400 insertions(+), 400 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/gchub_v9_0.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/gchub_v9_0.h > delete mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > delete mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile > b/drivers/gpu/drm/amd/amdgpu/Makefile > index 1143f1a..04d3952 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -48,7 +48,7 @@ amdgpu-y += \ > amdgpu-y += \ > gmc_v7_0.o \ > gmc_v8_0.o \ > - gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o > + gchub_v9_0.o mmhub_v1_0.o gmc_v9_0.o > > # add IH block > amdgpu-y += \ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > index 400f3ff..1177dc8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > @@ -2494,7 +2494,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct > amdgpu_vm *vm, > vm->vm_context = vm_context; > if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { > struct amdgpu_vm_id_manager *id_mgr = > - &adev->vm_manager.id_mgr[AMDGPU_GFXHUB]; > + &adev->vm_manager.id_mgr[AMDGPU_GCHUB]; > > mutex_lock(&id_mgr->lock); > > @@ -2564,7 +2564,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct > amdgpu_vm *vm) > > if (vm->vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { > struct amdgpu_vm_id_manager *id_mgr = > - &adev->vm_manager.id_mgr[AMDGPU_GFXHUB]; > + &adev->vm_manager.id_mgr[AMDGPU_GCHUB]; > > mutex_lock(&id_mgr->lock); > WARN(adev->vm_manager.n_compute_vms == 0, "Unbalanced number of > Compute VMs"); > @@ -2699,14 +2699,14 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void > *data, struct drm_file *filp) > > switch (args->in.op) { > case AMDGPU_VM_OP_RESERVE_VMID: > - /* current, we only have requirement to reserve vmid from > gfxhub */ > + /* current, we only have requirement to reserve vmid from gchub > */ > r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, > - AMDGPU_GFXHUB); > + AMDGPU_GCHUB); > if (r) > return r; > break; > case AMDGPU_VM_OP_UNRESERVE_VMID: > - amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); > + amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GCHUB); > break; > default: > return -EINVAL; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > index 8bc173a..d27240a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -79,7 +79,7 @@ struct amdgpu_bo_list_entry; > > /* max number of VMHUB */ > #define AMDGPU_MAX_VMHUBS 2 > -#define AMDGPU_GFXHUB 0 > +#define AMDGPU_GCHUB 0 > #define AMDGPU_MMHUB 1 > > /* hardcode that limit for now */ > diff --git a/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.c > new file mode 100644 > index 0000000..44945f0 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.c > @@ -0,0 +1,343 @@ > +/* > + * Copyright 2016 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > +#include "amdgpu.h" > +#include "gchub_v9_0.h" > + > +#include "vega10/soc15ip.h" > +#include "vega10/GC/gc_9_0_offset.h" > +#include "vega10/GC/gc_9_0_sh_mask.h" > +#include "vega10/GC/gc_9_0_default.h" > +#include "vega10/vega10_enum.h" > + > +#include "soc15_common.h" > + > +u64 gchub_v9_0_get_mc_fb_offset(struct amdgpu_device *adev) > +{ > + return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; > +} > + > +static void gchub_v9_0_init_gart_pt_regs(struct amdgpu_device *adev) > +{ > + uint64_t value; > + > + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); > + value = adev->gart.table_addr - adev->mc.vram_start > + + adev->vm_manager.vram_base_offset; > + value &= 0x0000FFFFFFFFF000ULL; > + value |= 0x1; /*valid bit*/ > + > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, > + lower_32_bits(value)); > + > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, > + upper_32_bits(value)); > +} > + > +static void gchub_v9_0_init_gart_aperture_regs(struct amdgpu_device *adev) > +{ > + gchub_v9_0_init_gart_pt_regs(adev); > + > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, > + (u32)(adev->mc.gart_start >> 12)); > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, > + (u32)(adev->mc.gart_start >> 44)); > + > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, > + (u32)(adev->mc.gart_end >> 12)); > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, > + (u32)(adev->mc.gart_end >> 44)); > +} > + > +static void gchub_v9_0_init_system_aperture_regs(struct amdgpu_device *adev) > +{ > + uint64_t value; > + > + /* Disable AGP. */ > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); > + > + /* Program the system aperture low logical page number. */ > + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, > + adev->mc.vram_start >> 18); > + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, > + adev->mc.vram_end >> 18); > + > + /* Set default page address. */ > + value = adev->vram_scratch.gpu_addr - adev->mc.vram_start > + + adev->vm_manager.vram_base_offset; > + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, > + (u32)(value >> 12)); > + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, > + (u32)(value >> 44)); > + > + /* Program "protection fault". */ > + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, > + (u32)(adev->dummy_page.addr >> 12)); > + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > + (u32)((u64)adev->dummy_page.addr >> 44)); > + > + WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, > + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > +} > + > +static void gchub_v9_0_init_tlb_regs(struct amdgpu_device *adev) > +{ > + uint32_t tmp; > + > + /* Setup TLB control */ > + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); > + > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > + ENABLE_ADVANCED_DRIVER_MODEL, 1); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > + MTYPE, MTYPE_UC);/* XXX for emulation. */ > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); > + > + WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); > +} > + > +static void gchub_v9_0_init_cache_regs(struct amdgpu_device *adev) > +{ > + uint32_t tmp; > + > + /* Setup L2 cache */ > + tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); > + /* XXX for emulation, Refer to closed source code.*/ > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, > + 0); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); > + WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); > + > + tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); > + WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); > + > + tmp = mmVM_L2_CNTL3_DEFAULT; > + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); > + > + tmp = mmVM_L2_CNTL4_DEFAULT; > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > + WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); > +} > + > +static void gchub_v9_0_enable_system_domain(struct amdgpu_device *adev) > +{ > + uint32_t tmp; > + > + tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); > +} > + > +static void gchub_v9_0_disable_identity_aperture(struct amdgpu_device *adev) > +{ > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, > + 0XFFFFFFFF); > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, > + 0x0000000F); > + > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, > + 0); > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, > + 0); > + > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); > + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); > + > +} > + > +static void gchub_v9_0_setup_vmid_config(struct amdgpu_device *adev) > +{ > + int i; > + uint32_t tmp; > + > + for (i = 0; i <= 14; i++) { > + tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > + adev->vm_manager.num_level); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + PAGE_TABLE_BLOCK_SIZE, > + adev->vm_manager.block_size - 9); > + /* Send no-retry XNACK on fault to suppress VM fault storm. */ > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); > + WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); > + WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); > + WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, > + lower_32_bits(adev->vm_manager.max_pfn - 1)); > + WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, > + upper_32_bits(adev->vm_manager.max_pfn - 1)); > + } > +} > + > +static void gchub_v9_0_program_invalidation(struct amdgpu_device *adev) > +{ > + unsigned i; > + > + for (i = 0 ; i < 18; ++i) { > + WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, > + 2 * i, 0xffffffff); > + WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, > + 2 * i, 0x1f); > + } > +} > + > +int gchub_v9_0_gart_enable(struct amdgpu_device *adev) > +{ > + if (amdgpu_sriov_vf(adev)) { > + /* > + * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are > + * VF copy registers so vbios post doesn't program them, for > + * SRIOV driver need to program them > + */ > + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, > + adev->mc.vram_start >> 24); > + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, > + adev->mc.vram_end >> 24); > + } > + > + /* GART Enable. */ > + gchub_v9_0_init_gart_aperture_regs(adev); > + gchub_v9_0_init_system_aperture_regs(adev); > + gchub_v9_0_init_tlb_regs(adev); > + gchub_v9_0_init_cache_regs(adev); > + > + gchub_v9_0_enable_system_domain(adev); > + gchub_v9_0_disable_identity_aperture(adev); > + gchub_v9_0_setup_vmid_config(adev); > + gchub_v9_0_program_invalidation(adev); > + > + return 0; > +} > + > +void gchub_v9_0_gart_disable(struct amdgpu_device *adev) > +{ > + u32 tmp; > + u32 i; > + > + /* Disable all tables */ > + for (i = 0; i < 16; i++) > + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); > + > + /* Setup TLB control */ > + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); > + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); > + tmp = REG_SET_FIELD(tmp, > + MC_VM_MX_L1_TLB_CNTL, > + ENABLE_ADVANCED_DRIVER_MODEL, > + 0); > + WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); > + > + /* Setup L2 cache */ > + WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); > + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); > +} > + > +/** > + * gchub_v9_0_set_fault_enable_default - update GART/VM fault handling > + * > + * @adev: amdgpu_device pointer > + * @value: true redirects VM faults to the default page > + */ > +void gchub_v9_0_set_fault_enable_default(struct amdgpu_device *adev, > + bool value) > +{ > + u32 tmp; > + tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, > + VM_L2_PROTECTION_FAULT_CNTL, > + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, > + value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); > +} > + > +void gchub_v9_0_init(struct amdgpu_device *adev) > +{ > + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GCHUB]; > + > + hub->ctx0_ptb_addr_lo32 = > + SOC15_REG_OFFSET(GC, 0, > + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); > + hub->ctx0_ptb_addr_hi32 = > + SOC15_REG_OFFSET(GC, 0, > + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); > + hub->vm_inv_eng0_req = > + SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); > + hub->vm_inv_eng0_ack = > + SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); > + hub->vm_context0_cntl = > + SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); > + hub->vm_l2_pro_fault_status = > + SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); > + hub->vm_l2_pro_fault_cntl = > + SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); > +} > diff --git a/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.h > b/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.h > new file mode 100644 > index 0000000..2e4ea4d > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/gchub_v9_0.h > @@ -0,0 +1,36 @@ > +/* > + * Copyright 2016 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#ifndef __GCHUB_V9_0_H__ > +#define __GCHUB_V9_0_H__ > + > +int gchub_v9_0_gart_enable(struct amdgpu_device *adev); > +void gchub_v9_0_gart_disable(struct amdgpu_device *adev); > +void gchub_v9_0_set_fault_enable_default(struct amdgpu_device *adev, > + bool value); > +void gchub_v9_0_init(struct amdgpu_device *adev); > +u64 gchub_v9_0_get_mc_fb_offset(struct amdgpu_device *adev); > +extern const struct amd_ip_funcs gchub_v9_0_ip_funcs; > +extern const struct amdgpu_ip_block_version gchub_v9_0_ip_block; > + > +#endif > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 3398d8b..c9258bd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -4179,7 +4179,7 @@ static const struct amdgpu_ring_funcs > gfx_v9_0_ring_funcs_gfx = { > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, > - .vmhub = AMDGPU_GFXHUB, > + .vmhub = AMDGPU_GCHUB, > .get_rptr = gfx_v9_0_ring_get_rptr_gfx, > .get_wptr = gfx_v9_0_ring_get_wptr_gfx, > .set_wptr = gfx_v9_0_ring_set_wptr_gfx, > @@ -4225,7 +4225,7 @@ static const struct amdgpu_ring_funcs > gfx_v9_0_ring_funcs_compute = { > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, > - .vmhub = AMDGPU_GFXHUB, > + .vmhub = AMDGPU_GCHUB, > .get_rptr = gfx_v9_0_ring_get_rptr_compute, > .get_wptr = gfx_v9_0_ring_get_wptr_compute, > .set_wptr = gfx_v9_0_ring_set_wptr_compute, > @@ -4255,7 +4255,7 @@ static const struct amdgpu_ring_funcs > gfx_v9_0_ring_funcs_kiq = { > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, > - .vmhub = AMDGPU_GFXHUB, > + .vmhub = AMDGPU_GCHUB, > .get_rptr = gfx_v9_0_ring_get_rptr_compute, > .get_wptr = gfx_v9_0_ring_get_wptr_compute, > .set_wptr = gfx_v9_0_ring_set_wptr_compute, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > deleted file mode 100644 > index 008ad3d..0000000 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ /dev/null > @@ -1,343 +0,0 @@ > -/* > - * Copyright 2016 Advanced Micro Devices, Inc. > - * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > - * The above copyright notice and this permission notice shall be included in > - * all copies or substantial portions of the Software. > - * > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > - * OTHER DEALINGS IN THE SOFTWARE. > - * > - */ > -#include "amdgpu.h" > -#include "gfxhub_v1_0.h" > - > -#include "vega10/soc15ip.h" > -#include "vega10/GC/gc_9_0_offset.h" > -#include "vega10/GC/gc_9_0_sh_mask.h" > -#include "vega10/GC/gc_9_0_default.h" > -#include "vega10/vega10_enum.h" > - > -#include "soc15_common.h" > - > -u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) > -{ > - return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; > -} > - > -static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) > -{ > - uint64_t value; > - > - BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); > - value = adev->gart.table_addr - adev->mc.vram_start > - + adev->vm_manager.vram_base_offset; > - value &= 0x0000FFFFFFFFF000ULL; > - value |= 0x1; /*valid bit*/ > - > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, > - lower_32_bits(value)); > - > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, > - upper_32_bits(value)); > -} > - > -static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) > -{ > - gfxhub_v1_0_init_gart_pt_regs(adev); > - > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, > - (u32)(adev->mc.gart_start >> 12)); > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, > - (u32)(adev->mc.gart_start >> 44)); > - > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, > - (u32)(adev->mc.gart_end >> 12)); > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, > - (u32)(adev->mc.gart_end >> 44)); > -} > - > -static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) > -{ > - uint64_t value; > - > - /* Disable AGP. */ > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); > - > - /* Program the system aperture low logical page number. */ > - WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, > - adev->mc.vram_start >> 18); > - WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, > - adev->mc.vram_end >> 18); > - > - /* Set default page address. */ > - value = adev->vram_scratch.gpu_addr - adev->mc.vram_start > - + adev->vm_manager.vram_base_offset; > - WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, > - (u32)(value >> 12)); > - WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, > - (u32)(value >> 44)); > - > - /* Program "protection fault". */ > - WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, > - (u32)(adev->dummy_page.addr >> 12)); > - WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > - (u32)((u64)adev->dummy_page.addr >> 44)); > - > - WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > -} > - > -static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) > -{ > - uint32_t tmp; > - > - /* Setup TLB control */ > - tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); > - > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > - ENABLE_ADVANCED_DRIVER_MODEL, 1); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > - SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, > - MTYPE, MTYPE_UC);/* XXX for emulation. */ > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); > - > - WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); > -} > - > -static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) > -{ > - uint32_t tmp; > - > - /* Setup L2 cache */ > - tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); > - /* XXX for emulation, Refer to closed source code.*/ > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, > - 0); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); > - WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); > - > - tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); > - WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); > - > - tmp = mmVM_L2_CNTL3_DEFAULT; > - WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); > - > - tmp = mmVM_L2_CNTL4_DEFAULT; > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > - WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); > -} > - > -static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) > -{ > - uint32_t tmp; > - > - tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); > -} > - > -static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) > -{ > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, > - 0XFFFFFFFF); > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, > - 0x0000000F); > - > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, > - 0); > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, > - 0); > - > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); > - WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); > - > -} > - > -static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) > -{ > - int i; > - uint32_t tmp; > - > - for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > - adev->vm_manager.num_level); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - PAGE_TABLE_BLOCK_SIZE, > - adev->vm_manager.block_size - 9); > - /* Send no-retry XNACK on fault to suppress VM fault storm. */ > - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > - RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > - WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); > - WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); > - WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); > - WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, > - lower_32_bits(adev->vm_manager.max_pfn - 1)); > - WREG32_SOC15_OFFSET(GC, 0, > mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, > - upper_32_bits(adev->vm_manager.max_pfn - 1)); > - } > -} > - > -static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) > -{ > - unsigned i; > - > - for (i = 0 ; i < 18; ++i) { > - WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, > - 2 * i, 0xffffffff); > - WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, > - 2 * i, 0x1f); > - } > -} > - > -int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) > -{ > - if (amdgpu_sriov_vf(adev)) { > - /* > - * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are > - * VF copy registers so vbios post doesn't program them, for > - * SRIOV driver need to program them > - */ > - WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, > - adev->mc.vram_start >> 24); > - WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, > - adev->mc.vram_end >> 24); > - } > - > - /* GART Enable. */ > - gfxhub_v1_0_init_gart_aperture_regs(adev); > - gfxhub_v1_0_init_system_aperture_regs(adev); > - gfxhub_v1_0_init_tlb_regs(adev); > - gfxhub_v1_0_init_cache_regs(adev); > - > - gfxhub_v1_0_enable_system_domain(adev); > - gfxhub_v1_0_disable_identity_aperture(adev); > - gfxhub_v1_0_setup_vmid_config(adev); > - gfxhub_v1_0_program_invalidation(adev); > - > - return 0; > -} > - > -void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) > -{ > - u32 tmp; > - u32 i; > - > - /* Disable all tables */ > - for (i = 0; i < 16; i++) > - WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); > - > - /* Setup TLB control */ > - tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); > - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); > - tmp = REG_SET_FIELD(tmp, > - MC_VM_MX_L1_TLB_CNTL, > - ENABLE_ADVANCED_DRIVER_MODEL, > - 0); > - WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); > - > - /* Setup L2 cache */ > - WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); > - WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); > -} > - > -/** > - * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling > - * > - * @adev: amdgpu_device pointer > - * @value: true redirects VM faults to the default page > - */ > -void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, > - bool value) > -{ > - u32 tmp; > - tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, > - VM_L2_PROTECTION_FAULT_CNTL, > - TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, > - value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); > -} > - > -void gfxhub_v1_0_init(struct amdgpu_device *adev) > -{ > - struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; > - > - hub->ctx0_ptb_addr_lo32 = > - SOC15_REG_OFFSET(GC, 0, > - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); > - hub->ctx0_ptb_addr_hi32 = > - SOC15_REG_OFFSET(GC, 0, > - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); > - hub->vm_inv_eng0_req = > - SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); > - hub->vm_inv_eng0_ack = > - SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); > - hub->vm_context0_cntl = > - SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); > - hub->vm_l2_pro_fault_status = > - SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); > - hub->vm_l2_pro_fault_cntl = > - SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); > -} > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h > deleted file mode 100644 > index d2dbb08..0000000 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h > +++ /dev/null > @@ -1,36 +0,0 @@ > -/* > - * Copyright 2016 Advanced Micro Devices, Inc. > - * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > - * The above copyright notice and this permission notice shall be included in > - * all copies or substantial portions of the Software. > - * > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > - * OTHER DEALINGS IN THE SOFTWARE. > - * > - */ > - > -#ifndef __GFXHUB_V1_0_H__ > -#define __GFXHUB_V1_0_H__ > - > -int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev); > -void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev); > -void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, > - bool value); > -void gfxhub_v1_0_init(struct amdgpu_device *adev); > -u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev); > -extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs; > -extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block; > - > -#endif > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e9a5209..c880001 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -35,7 +35,7 @@ > > #include "nbio_v6_1.h" > #include "nbio_v7_0.h" > -#include "gfxhub_v1_0.h" > +#include "gchub_v9_0.h" > #include "mmhub_v1_0.h" > > #define mmDF_CS_AON0_DramBaseAddress0 > 0x0044 > @@ -97,7 +97,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct > amdgpu_device *adev, > } > > /* GFX HUB */ > - hub = &adev->vmhub[AMDGPU_GFXHUB]; > + hub = &adev->vmhub[AMDGPU_GCHUB]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); > @@ -116,7 +116,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct > amdgpu_device *adev, > } > > /* GFX HUB */ > - hub = &adev->vmhub[AMDGPU_GFXHUB]; > + hub = &adev->vmhub[AMDGPU_GCHUB]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); > @@ -150,7 +150,7 @@ static int gmc_v9_0_process_interrupt(struct > amdgpu_device *adev, > if (printk_ratelimit()) { > dev_err(adev->dev, > "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u > pas_id:%u)\n", > - entry->vm_id_src ? "mmhub" : "gfxhub", > + entry->vm_id_src ? "mmhub" : "gchub", > entry->src_id, entry->ring_id, entry->vm_id, > entry->pas_id); > dev_err(adev->dev, " at page 0x%016llx from %d\n", > @@ -423,7 +423,7 @@ static void gmc_v9_0_vram_gtt_location(struct > amdgpu_device *adev, > amdgpu_gart_location(adev, mc); > /* base offset of vram pages */ > if (adev->flags & AMD_IS_APU) > - adev->vm_manager.vram_base_offset = > gfxhub_v1_0_get_mc_fb_offset(adev); > + adev->vm_manager.vram_base_offset = > gchub_v9_0_get_mc_fb_offset(adev); > else > adev->vm_manager.vram_base_offset = 0; > } > @@ -527,7 +527,7 @@ static int gmc_v9_0_sw_init(void *handle) > int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > - gfxhub_v1_0_init(adev); > + gchub_v9_0_init(adev); > mmhub_v1_0_init(adev); > > spin_lock_init(&adev->mc.invalidate_lock); > @@ -626,7 +626,7 @@ static int gmc_v9_0_sw_init(void *handle) > * amdgpu graphics/compute will use VMIDs 1-7 > * amdkfd will use VMIDs 8-15 > */ > - adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; > + adev->vm_manager.id_mgr[AMDGPU_GCHUB].num_ids = AMDGPU_NUM_OF_VMIDS; > adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; > > amdgpu_vm_manager_init(adev); > @@ -709,7 +709,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device > *adev) > break; > } > > - r = gfxhub_v1_0_gart_enable(adev); > + r = gchub_v9_0_gart_enable(adev); > if (r) > return r; > > @@ -730,7 +730,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device > *adev) > else > value = true; > > - gfxhub_v1_0_set_fault_enable_default(adev, value); > + gchub_v9_0_set_fault_enable_default(adev, value); > mmhub_v1_0_set_fault_enable_default(adev, value); > > gmc_v9_0_gart_flush_gpu_tlb(adev, 0); > @@ -764,7 +764,7 @@ static int gmc_v9_0_hw_init(void *handle) > */ > static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) > { > - gfxhub_v1_0_gart_disable(adev); > + gchub_v9_0_gart_disable(adev); > mmhub_v1_0_gart_disable(adev); > amdgpu_gart_table_vram_unpin(adev); > } > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c > b/drivers/gpu/drm/amd/amdgpu/soc15.c > index c184fe8..b8a5488 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -51,7 +51,7 @@ > #include "soc15_common.h" > #include "gfx_v9_0.h" > #include "gmc_v9_0.h" > -#include "gfxhub_v1_0.h" > +#include "gchub_v9_0.h" > #include "mmhub_v1_0.h" > #include "vega10_ih.h" > #include "sdma_v4_0.h" > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
