[PATCH 1/8] drm/amdgpu: Clear vce&uvd ring wptr for SRIOV

[Xiangliang . Yu]

From: Frank Min <frank....@amd.com>

MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.

Signed-off-by: Frank Min <frank....@amd.com>
Signed-off-by: Xiangliang.Yu <xiangliang...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++++-
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 987b958..e2b17cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -685,6 +685,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
        /* 4, set resp to zero */
        WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 
+       WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
+       adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
+       adev->uvd.ring_enc[0].wptr = 0;
+       adev->uvd.ring_enc[0].wptr_old = 0;
+
        /* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
        WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 
@@ -702,7 +707,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
                dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
                return -EBUSY;
        }
-       WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
 
        return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 1ecd6bb..9b1de6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
        /* 4, set resp to zero */
        WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
 
+       WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
+       adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
+       adev->vce.ring[0].wptr = 0;
+       adev->vce.ring[0].wptr_old = 0;
+
        /* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
        WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 
0x10000001);
 
@@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
                dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
                return -EBUSY;
        }
-       WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
 
        return 0;
 }
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx