From: Eric Yang <eric.ya...@amd.com>
Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.
Change-Id: I252b4fcf08cfb4ddf7242fab0d7d49c57b015b7d
Signed-off-by: Eric Yang <eric.ya...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 24f8c44..3118c24 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -822,8 +822,7 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[0] = v->phyclkv_min0p65;
if (dc->public.debug.disable_pipe_split) {
- v->max_dppclk[1] = v->max_dppclk_vnom0p8;
- v->max_dppclk[0] = v->max_dppclk_vnom0p8;
+ v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
if (v->voltage_override == dcn_bw_v_max0p9) {
--
2.7.4
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