[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Zhigang Luo <[email protected]>
-----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Victor Skvortsov Sent: Sunday, May 19, 2024 10:52 AM To: [email protected] Cc: Skvortsov, Victor <[email protected]> Subject: [PATCH 1/2] drm/amdgpu: Extend KIQ reg polling wait for VF Runtime KIQ interface to read/write registers in VF may take longer than expected for BM environment. Extend the timeout. Signed-off-by: Victor Skvortsov <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d749c6abdc5e..e8980b6009c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -348,9 +348,9 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, AMDGPU_CP_KIQ_IRQ_LAST }; -#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ +#define MAX_KIQ_REG_WAIT amdgpu_sriov_vf(adev) ? 50000 : 5000 /* in +usecs, extend for VF */ #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in +msecs, 5ms */ #define MAX_KIQ_REG_TRY 1000 int amdgpu_device_ip_set_clockgating_state(void *dev, -- 2.34.1
