GFX v9.4.3 uses mode1 reset, other ASICs choose mode2.

Signed-off-by: Tao Zhou <tao.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index 78dde62fb04a..816800555f7f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -164,7 +164,10 @@ static void event_interrupt_poison_consumption_v9(struct 
kfd_node *dev,
        case SOC15_IH_CLIENTID_SE3SH:
        case SOC15_IH_CLIENTID_UTCL2:
                block = AMDGPU_RAS_BLOCK__GFX;
-               reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 
4, 3))
+                       reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               else
+                       reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
                break;
        case SOC15_IH_CLIENTID_VMC:
        case SOC15_IH_CLIENTID_VMC1:
@@ -177,7 +180,10 @@ static void event_interrupt_poison_consumption_v9(struct 
kfd_node *dev,
        case SOC15_IH_CLIENTID_SDMA3:
        case SOC15_IH_CLIENTID_SDMA4:
                block = AMDGPU_RAS_BLOCK__SDMA;
-               reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 
4, 3))
+                       reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               else
+                       reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
                break;
        default:
                dev_warn(dev->adev->dev,
-- 
2.34.1

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