From: Tony Cheng <tony.ch...@amd.com>

Change-Id: I44037c65816a4adab4e852c1c0b476a56862cd2d
Signed-off-by: Tony Cheng <tony.ch...@amd.com>
Reviewed-by: Zeyu Fan <zeyu....@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 11 ++++++-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  3 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 12 ++++++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 38 ----------------------
 4 files changed, 23 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 80ee1ac32fee..7feb1ca9b8c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -170,7 +170,12 @@
        SR(DIO_MEM_PWR_CTRL), \
        SR(DCCG_GATE_DISABLE_CNTL), \
        SR(DCCG_GATE_DISABLE_CNTL2), \
-       SR(DCFCLK_CNTL)
+       SR(DCFCLK_CNTL),\
+       SR(DCFCLK_CNTL), \
+       SR(D1VGA_CONTROL), \
+       SR(D2VGA_CONTROL), \
+       SR(D3VGA_CONTROL), \
+       SR(D4VGA_CONTROL)
 #endif
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -236,6 +241,10 @@ struct dce_hwseq_registers {
        uint32_t MPC_CRC_RESULT_GB;
        uint32_t MPC_CRC_RESULT_C;
        uint32_t MPC_CRC_RESULT_AR;
+       uint32_t D1VGA_CONTROL;
+       uint32_t D2VGA_CONTROL;
+       uint32_t D3VGA_CONTROL;
+       uint32_t D4VGA_CONTROL;
 #endif
 };
  /* set field name */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index baafe6609d24..72e099953a05 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1198,7 +1198,8 @@ static void disable_vga_and_power_gate_all_controllers(
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                tg = dc->res_pool->timing_generators[i];
 
-               tg->funcs->disable_vga(tg);
+               if (tg->funcs->disable_vga)
+                       tg->funcs->disable_vga(tg);
 
                /* Enable CLOCK gating for each pipe BEFORE controller
                 * powergating. */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ce7da8864507..64f2fd0d539e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -163,6 +163,15 @@ static void enable_power_gating_plane(
        REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 }
 
+static void disable_vga(
+       struct dce_hwseq *hws)
+{
+       REG_WRITE(D1VGA_CONTROL, 0);
+       REG_WRITE(D2VGA_CONTROL, 0);
+       REG_WRITE(D3VGA_CONTROL, 0);
+       REG_WRITE(D4VGA_CONTROL, 0);
+}
+
 static void dpp_pg_control(
                struct dce_hwseq *hws,
                unsigned int dpp_inst,
@@ -312,6 +321,8 @@ static void dcn10_init_hw(struct core_dc *dc)
 
        bios_golden_init(dc);
 
+       disable_vga(dc->hwseq);
+
        for (i = 0; i < dc->link_count; i++) {
                /* Power up AND update implementation according to the
                 * required signal (which may be different from the
@@ -335,7 +346,6 @@ static void dcn10_init_hw(struct core_dc *dc)
                mpcc_cfg.top_of_tree = true;
                mpcc->funcs->set(mpcc, &mpcc_cfg);
 
-               tg->funcs->disable_vga(tg);
                /* Blank controller using driver code instead of
                 * command table.
                 */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index b2e796d87dac..0ef5d8f0625c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -447,43 +447,6 @@ static void tgn10_program_blank_color(
                        OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
 }
 
-/**
- * dcn10_dcn10_timing_generator_disable_vga
- * Turn OFF VGA Mode and Timing  - DxVGA_CONTROL
- * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors;
- */
-/* TODO FPGA FPGA setup is done by Diag which does not enable VGA mode.
- * VGA is disable by ASIC default. This function is not needed for
- * FPGA story.
- * usage:
- * init_hw  within dc.c
- * disable_vga_and_power_gate_all_controllers within dce110_hw_sequencer.c
- * We may move init_hw into DC specific so that we can remove
- * .disable_vga from upper layer stack
- */
-static void tgn10_disable_vga(
-                       struct timing_generator *tg)
-{
-       struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-
-       switch (tgn10->base.inst) {
-       case 0:
-               REG_WRITE(D1VGA_CONTROL, 0);
-               break;
-       case 1:
-               REG_WRITE(D2VGA_CONTROL, 0);
-               break;
-       case 2:
-               REG_WRITE(D2VGA_CONTROL, 0);
-               break;
-       case 3:
-               REG_WRITE(D4VGA_CONTROL, 0);
-               break;
-       default:
-               break;
-       }
-}
-
 static bool tgn10_validate_timing(
        struct timing_generator *tg,
        const struct dc_crtc_timing *timing)
@@ -1144,7 +1107,6 @@ static struct timing_generator_funcs dcn10_tg_funcs = {
                .set_blank = tgn10_set_blank,
                .is_blanked = tgn10_is_blanked,
                .set_blank_color = tgn10_program_blank_color,
-               .disable_vga = tgn10_disable_vga,
                .did_triggered_reset_occur = tgn10_did_triggered_reset_occur,
                .enable_reset_trigger = tgn10_enable_reset_trigger,
                .disable_reset_trigger = tgn10_disable_reset_trigger,
-- 
2.11.0

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