[PATCH 7/9] drm/amdgpu: Enable devcoredump for JPEG3_0_0

[Sathishkumar S]

Add register list and enable devcoredump for JPEG3_0_0

Signed-off-by: Sathishkumar S <sathishkumar.sundarar...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 39 ++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 4eca65ea9053..d95b62204745 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -34,10 +34,28 @@
 
 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET       0x401f
 
+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_3_0[] = {
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JPEG_POWER_STATUS),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JPEG_INT_STAT),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JRBC_RB_RPTR),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JRBC_RB_WPTR),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JRBC_RB_CNTL),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JRBC_RB_SIZE),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JRBC_STATUS),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmJPEG_DEC_ADDR_MODE),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JPEG_PITCH),
+       SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_JPEG_UV_PITCH),
+};
+
 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
 static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
+static void jpeg_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block);
+static void jpeg_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct 
drm_printer *p);
 
 /**
  * jpeg_v3_0_early_init - set function pointers
@@ -112,6 +130,12 @@ static int jpeg_v3_0_sw_init(struct amdgpu_ip_block 
*ip_block)
        adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
        adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, 
mmUVD_JPEG_PITCH);
 
+       adev->jpeg.ip_dump = kcalloc(adev->jpeg.num_jpeg_inst * 
ARRAY_SIZE(jpeg_reg_list_3_0),
+                                    sizeof(uint32_t), GFP_KERNEL);
+       if (!adev->jpeg.ip_dump)
+               DRM_ERROR("Failed to allocate memory for JPEG IP Dump\n");
+
+
        return 0;
 }
 
@@ -133,6 +157,8 @@ static int jpeg_v3_0_sw_fini(struct amdgpu_ip_block 
*ip_block)
 
        r = amdgpu_jpeg_sw_fini(adev);
 
+       kfree(adev->jpeg.ip_dump);
+
        return r;
 }
 
@@ -530,6 +556,17 @@ static int jpeg_v3_0_process_interrupt(struct 
amdgpu_device *adev,
        return 0;
 }
 
+static void jpeg_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
+{
+       amdgpu_jpeg_dump_ip_state(ip_block, jpeg_reg_list_3_0, 
ARRAY_SIZE(jpeg_reg_list_3_0));
+}
+
+static void jpeg_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct 
drm_printer *p)
+{
+       amdgpu_jpeg_print_ip_state(ip_block, p, jpeg_reg_list_3_0,
+                                  ARRAY_SIZE(jpeg_reg_list_3_0));
+}
+
 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
        .name = "jpeg_v3_0",
        .early_init = jpeg_v3_0_early_init,
@@ -543,6 +580,8 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
        .wait_for_idle = jpeg_v3_0_wait_for_idle,
        .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
        .set_powergating_state = jpeg_v3_0_set_powergating_state,
+       .dump_ip_state = jpeg_v3_0_dump_ip_state,
+       .print_ip_state = jpeg_v3_0_print_ip_state,
 };
 
 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
-- 
2.25.1