[PATCH 09/27] drm/amd/display: Revert "Increase halt timeout for DMCUB to 1s"

[Wayne Lin]

From: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>

This reverts commit 7f4d49ac3944 ("drm/amd/display: Increase halt
timeout for DMCUB to 1s")

There's two issues here:
1. Each poll is closer to 10us than 1us so it stalls for 15s on PNP.
2. We're reading the wrong scratch register to check for the HALT code.

Reviewed-by: Dillon Varone <dillon.var...@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Signed-off-by: Wayne Lin <wayne....@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 15 +++++----------
 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c |  2 +-
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index 1fac75dfc650..3d0bba602b53 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -83,8 +83,8 @@ static inline void dmub_dcn31_translate_addr(const union 
dmub_addr *addr_in,
 void dmub_dcn31_reset(struct dmub_srv *dmub)
 {
        union dmub_gpint_data_register cmd;
-       const uint32_t timeout = 1000000;
-       uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
+       const uint32_t timeout = 100;
+       uint32_t in_reset, scratch, i, pwait_mode;
 
        REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
 
@@ -125,14 +125,9 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)
                /* Force reset in case we timed out, DMCUB is likely hung. */
        }
 
-       REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
-
-       if (is_enabled) {
-               REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
-               REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
-               REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
-       }
-
+       REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+       REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+       REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
        REG_WRITE(DMCUB_INBOX1_RPTR, 0);
        REG_WRITE(DMCUB_INBOX1_WPTR, 0);
        REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 652173b10401..e5e77bd3c31e 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -88,7 +88,7 @@ static inline void dmub_dcn35_translate_addr(const union 
dmub_addr *addr_in,
 void dmub_dcn35_reset(struct dmub_srv *dmub)
 {
        union dmub_gpint_data_register cmd;
-       const uint32_t timeout = 1000000;
+       const uint32_t timeout = 100;
        uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
 
        REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
-- 
2.37.3