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@Yadav, Arvind<mailto:[email protected]>



-----Original Message-----
From: Sunil Khatri <[email protected]>
Sent: Wednesday, May 7, 2025 3:00 PM
To: [email protected]; Deucher, Alexander 
<[email protected]>; Koenig, Christian <[email protected]>
Cc: Dan Carpenter <[email protected]>; Khatri, Sunil 
<[email protected]>
Subject: [PATCH v2] drm/amdgpu: fix the indentation



fix the indentation

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:6992 gfx_v11_ip_dump



compiler: gcc-11 (Debian 11.3.0-12) 11.3.0

| Reported-by: kernel test robot <[email protected]<mailto:[email protected]>>

| Reported-by: Dan Carpenter 
<[email protected]<mailto:[email protected]>>

| Closes: https://lore.kernel.org/r/[email protected]/



Signed-off-by: Sunil Khatri <[email protected]<mailto:[email protected]>>

---

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---

1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

index 3f4ee4b3b0a4..fe21393e155d 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

@@ -7094,9 +7094,12 @@ static void gfx_v11_ip_dump(struct amdgpu_ip_block 
*ip_block)

                                               /* ME0 is for GFX so start from 
1 for CP */

                                               soc21_grbm_select(adev, 
adev->gfx.me.num_me + i, j, k, 0);

                                               for (reg = 0; reg < reg_count; 
reg++) {

-                                                           if (i && 
gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)

-                                                           
adev->gfx.ip_dump_compute_queues[index + reg] =

-                                                                       
RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME2_HEADER_DUMP));

+                                                          if (i &&

+                                                              
gc_cp_reg_list_11[reg].reg_offset ==

+                                                                          
regCP_MEC_ME1_HEADER_DUMP)

+                                                                      
adev->gfx.ip_dump_compute_queues[index + reg] =

+                                                                               
   RREG32(SOC15_REG_OFFSET(GC, 0,

+                                                                               
   regCP_MEC_ME2_HEADER_DUMP));

                                                           else

                                                                       
adev->gfx.ip_dump_compute_queues[index + reg] =

                                                                                
   RREG32(SOC15_REG_ENTRY_OFFSET(

--

2.34.1


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