The addition of register read-back in VCN v2.5 is intended to prevent potential race conditions.
Signed-off-by: David (Ming Qiang) Wu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 3eec1b8feaee..beffe0795ca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1158,6 +1158,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); + /* Keeping one read-back to ensure all register writes are done, otherwise + * it may introduce race conditions + */ + RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR); + return 0; } @@ -1343,6 +1348,11 @@ static int vcn_v2_5_start(struct amdgpu_vcn_inst *vinst) WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; + /* Keeping one read-back to ensure all register writes are done, otherwise + * it may introduce race conditions + */ + RREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR); + return 0; } -- 2.49.0
