added registers to enable jpeg ras
Signed-off-by: Mangesh Gadre <[email protected]>
Reviewed-by: Stanley.Yang <[email protected]>
---
.../drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h | 4 ++++
.../drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
index f45155280ff5..72a118b2af69 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
@@ -1070,6 +1070,10 @@
#define regUVD_RAS_VCPU_VCODEC_STATUS
0x0057
#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX
1
#define regUVD_SCRATCH15
0x005c
+#define regUVD_RAS_JPEG0_STATUS
0x0059
+#define regUVD_RAS_JPEG0_STATUS_BASE_IDX
1
+#define regUVD_RAS_JPEG1_STATUS
0x005a
+#define regUVD_RAS_JPEG1_STATUS_BASE_IDX
1
#define regUVD_SCRATCH15_BASE_IDX
1
#define regUVD_VERSION
0x005d
#define regUVD_VERSION_BASE_IDX
1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
index eb8ff9de5826..c78b09d6fbae 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
@@ -5720,6 +5720,16 @@
#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK
0x7FFFFFFFL
#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK
0x80000000L
+//UVD_RAS_JPEG0_STATUS
+#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT
0x0
+#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT
0x1f
+#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK
0x7FFFFFFFL
+#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK
0x80000000L
+//UVD_RAS_JPEG1_STATUS
+#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT
0x0
+#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT
0x1f
+#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK
0x7FFFFFFFL
+#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK
0x80000000L
//UVD_SCRATCH15
#define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT
0x0
#define UVD_SCRATCH15__SCRATCH15_DATA_MASK
0xFFFFFFFFL
--
2.34.1
