[v3 3/9] drm/amdgpu/mes11: implement detect and reset callback

[Jesse . Zhang]

From: Alex Deucher <alexander.deuc...@amd.com>

Implement support for the hung queue detect and reset
functionality.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 31 ++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c9eba537de09..cded31da3f31 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -66,6 +66,8 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
 #define GFX_MES_DRAM_SIZE      0x80000
 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)
 
+#define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 4
+
 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
@@ -783,6 +785,32 @@ static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,
                        offsetof(union MESAPI__RESET, api_status));
 }
 
+static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes,
+                                                 struct 
mes_detect_and_reset_queue_input *input)
+{
+       union MESAPI__RESET mes_reset_queue_pkt;
+
+       memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
+
+       mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
+       mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
+       mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+       mes_reset_queue_pkt.queue_type =
+               convert_to_mes_queue_type(input->queue_type);
+       mes_reset_queue_pkt.doorbell_offset_addr =
+               mes->hung_queue_db_array_gpu_addr;
+
+       if (input->detect_only)
+               mes_reset_queue_pkt.hang_detect_only = 1;
+       else
+               mes_reset_queue_pkt.hang_detect_then_reset = 1;
+
+       return mes_v11_0_submit_pkt_and_poll_completion(mes,
+                       &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
+                       offsetof(union MESAPI__RESET, api_status));
+}
+
 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
        .add_hw_queue = mes_v11_0_add_hw_queue,
        .remove_hw_queue = mes_v11_0_remove_hw_queue,
@@ -792,6 +820,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
        .resume_gang = mes_v11_0_resume_gang,
        .misc_op = mes_v11_0_misc_op,
        .reset_hw_queue = mes_v11_0_reset_hw_queue,
+       .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues,
 };
 
 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
@@ -1682,6 +1711,8 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block 
*ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        int pipe, r;
 
+       adev->mes.hung_queue_db_array_size =
+               MES11_HUNG_DB_OFFSET_ARRAY_SIZE;
        for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
                if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
                        continue;
-- 
2.49.0