On 27.06.25 05:39, Alex Deucher wrote:
> Need to reinit the ring before remapping it and all of
> the KIQ handling needs to be within the kiq lock.
>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +++++++++++++++-----
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 8c377ecbb8a75..5e099b5dc9a3c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9544,7 +9544,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
>
> spin_lock_irqsave(&kiq->ring_lock, flags);
>
> - if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size))
> {
> + if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {
> spin_unlock_irqrestore(&kiq->ring_lock, flags);
> return -ENOMEM;
> }
> @@ -9564,12 +9564,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring
> *ring,
> 0, 1, 0x20);
> gfx_v10_0_ring_emit_reg_wait(kiq_ring,
> SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET),
> 0, 0xffffffff);
> - kiq->pmf->kiq_map_queues(kiq_ring, ring);
> amdgpu_ring_commit(kiq_ring);
> -
> - spin_unlock_irqrestore(&kiq->ring_lock, flags);
> -
> r = amdgpu_ring_test_ring(kiq_ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> if (r)
> return r;
>
> @@ -9579,6 +9576,19 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring
> *ring,
> return r;
> }
>
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> +
> + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> + return -ENOMEM;
> + }
> + kiq->pmf->kiq_map_queues(kiq_ring, ring);
> + amdgpu_ring_commit(kiq_ring);
> + r = amdgpu_ring_test_ring(kiq_ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> + if (r)
> + return r;
> +
> r = amdgpu_ring_test_ring(ring);
> if (r)
> return r;
