On Sun, Jul 6, 2025 at 10:59 AM Rodrigo Siqueira <sique...@igalia.com> wrote:
>
> On 07/01, Alex Deucher wrote:
> > Re-emit the unprocessed state after resetting the queue.
> >
> > Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 41 ++++----------------------
> > 1 file changed, 6 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 5e099b5dc9a3c..65429afb33ec3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -9046,21 +9046,6 @@ static void
> > gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> > ref, mask);
> > }
> >
> > -static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
> > - unsigned int vmid)
> > -{
> > - struct amdgpu_device *adev = ring->adev;
> > - uint32_t value = 0;
> > -
> > - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
> > - value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
> > - value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
> > - value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
> > - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> > - WREG32_SOC15(GC, 0, mmSQ_CMD, value);
> > - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> > -}
> > -
>
> You are eliminating the gfx_v10_0_ring_soft_recovery here, but why you
> did not remove it in the GFX9 (previous commit)?
gfx9 doesn't implement graphics reset yet so we still need soft recovery.
>
> Also, I suppose the new recovery method from this series will replace
> this soft_recovery, right? If so, I suggest you include this information
> in the commit message.
Correct. Will update the message.
Alex
>
> Thanks
>
> > static void
> > gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
> > uint32_t me, uint32_t pipe,
> > @@ -9540,7 +9525,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring
> > *ring,
> > if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
> > return -EINVAL;
> >
> > - drm_sched_wqueue_stop(&ring->sched);
> > + amdgpu_ring_reset_helper_begin(ring, timedout_fence);
> >
> > spin_lock_irqsave(&kiq->ring_lock, flags);
> >
> > @@ -9589,12 +9574,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring
> > *ring,
> > if (r)
> > return r;
> >
> > - r = amdgpu_ring_test_ring(ring);
> > - if (r)
> > - return r;
> > - amdgpu_fence_driver_force_completion(ring);
> > - drm_sched_wqueue_start(&ring->sched);
> > - return 0;
> > + return amdgpu_ring_reset_helper_end(ring, timedout_fence);
> > }
> >
> > static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
> > @@ -9613,7 +9593,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring
> > *ring,
> > if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
> > return -EINVAL;
> >
> > - drm_sched_wqueue_stop(&ring->sched);
> > + amdgpu_ring_reset_helper_begin(ring, timedout_fence);
> >
> > spin_lock_irqsave(&kiq->ring_lock, flags);
> >
> > @@ -9625,9 +9605,8 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring
> > *ring,
> > kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
> > 0, 0);
> > amdgpu_ring_commit(kiq_ring);
> > - spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > -
> > r = amdgpu_ring_test_ring(kiq_ring);
> > + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > if (r)
> > return r;
> >
> > @@ -9663,18 +9642,12 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring
> > *ring,
> > }
> > kiq->pmf->kiq_map_queues(kiq_ring, ring);
> > amdgpu_ring_commit(kiq_ring);
> > - spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > -
> > r = amdgpu_ring_test_ring(kiq_ring);
> > + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > if (r)
> > return r;
> >
> > - r = amdgpu_ring_test_ring(ring);
> > - if (r)
> > - return r;
> > - amdgpu_fence_driver_force_completion(ring);
> > - drm_sched_wqueue_start(&ring->sched);
> > - return 0;
> > + return amdgpu_ring_reset_helper_end(ring, timedout_fence);
> > }
> >
> > static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct
> > drm_printer *p)
> > @@ -9909,7 +9882,6 @@ static const struct amdgpu_ring_funcs
> > gfx_v10_0_ring_funcs_gfx = {
> > .emit_wreg = gfx_v10_0_ring_emit_wreg,
> > .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
> > .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
> > - .soft_recovery = gfx_v10_0_ring_soft_recovery,
> > .emit_mem_sync = gfx_v10_0_emit_mem_sync,
> > .reset = gfx_v10_0_reset_kgq,
> > .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
> > @@ -9950,7 +9922,6 @@ static const struct amdgpu_ring_funcs
> > gfx_v10_0_ring_funcs_compute = {
> > .emit_wreg = gfx_v10_0_ring_emit_wreg,
> > .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
> > .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
> > - .soft_recovery = gfx_v10_0_ring_soft_recovery,
> > .emit_mem_sync = gfx_v10_0_emit_mem_sync,
> > .reset = gfx_v10_0_reset_kcq,
> > .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
> > --
> > 2.50.0
> >
>
> --
> Rodrigo Siqueira
