[v4 02/11] drm/amd/amdgpu: Implement HQD PQ address retrieval for GFX12

[Jesse . Zhang]

This commit adds HQD PQ address lookup functionality for GFX12.

Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 7220ed2fa2a3..f213eb5c6694 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3051,6 +3051,51 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device 
*adev, void *m,
        return 0;
 }
 
+static uint64_t gfx_v12_0_hqd_get_pq_addr(struct amdgpu_device *adev, uint32_t 
queue_type,
+                    uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
+                    uint32_t xcc_id, uint32_t *vmid)
+{
+       uint32_t low = 0, high = 0, active = 0;
+       uint64_t queue_addr = 0;
+
+       mutex_lock(&adev->srbm_mutex);
+       /* Enter safe mode to safely access HQD registers */
+       amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
+
+
+       /* Select the specific ME/PIPE/QUEUE to access its HQD registers */
+       soc24_grbm_select(adev, me_id, pipe_id, queue_id, 0);
+
+       if (queue_type == AMDGPU_RING_TYPE_GFX) {
+               active = RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE);
+               if (!(active & 1))
+                       goto unlock_out;
+
+               *vmid = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
+               low = RREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE);
+               high = RREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI);
+
+               queue_addr = (((uint64_t)high << 32) | low) << 8;
+       } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
+               active = RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE);
+               if (!(active & 1))
+                       goto unlock_out;
+
+               *vmid = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
+               low = RREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE);
+               high = RREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI);
+
+               queue_addr = (((uint64_t)high << 32) | low) << 8;
+       }
+
+unlock_out:
+       soc24_grbm_select(adev, 0, 0, 0, 0);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
+       mutex_unlock(&adev->srbm_mutex);
+
+       return queue_addr;
+}
+
 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
 {
        struct amdgpu_device *adev = ring->adev;
@@ -5694,11 +5739,15 @@ static void gfx_v12_0_set_mqd_funcs(struct 
amdgpu_device *adev)
                sizeof(struct v12_gfx_mqd);
        adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
                gfx_v12_0_gfx_mqd_init;
+       adev->mqds[AMDGPU_HW_IP_GFX].hqd_get_pq_addr =
+               gfx_v12_0_hqd_get_pq_addr;
        /* set compute eng mqd */
        adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
                sizeof(struct v12_compute_mqd);
        adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
                gfx_v12_0_compute_mqd_init;
+       adev->mqds[AMDGPU_HW_IP_COMPUTE].hqd_get_pq_addr =
+               gfx_v12_0_hqd_get_pq_addr;
 }
 
 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device 
*adev,
-- 
2.49.0