[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu <leo....@amd.com>
> -----Original Message-----
> From: Sundararaju, Sathishkumar <sathishkumar.sundarar...@amd.com>
> Sent: July 14, 2025 2:01 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo <leo....@amd.com>; Sundararaju, Sathishkumar
> <sathishkumar.sundarar...@amd.com>
> Subject: [PATCH] drm/amdgpu: Check vcn sram load return value
>
> Log an error when vcn sram load fails in indirect mode and return the same
> error value.
>
> Signed-off-by: Sathishkumar S <sathishkumar.sundarar...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 11 ++++++++---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 11 ++++++++---
> 8 files changed, 63 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 148b651be7ca..a17629b7f4e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -851,6 +851,7 @@ static int vcn_v2_0_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst, bool indirect)
> volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst-
> >fw_shared.cpu_addr;
> struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> uint32_t rb_bufsz, tmp;
> + int ret;
>
> vcn_v2_0_enable_static_power_gating(vinst);
>
> @@ -934,8 +935,13 @@ static int vcn_v2_0_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst, bool indirect)
> UVD, 0, mmUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, 0, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, 0, 0);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> /* force RBC into idle state */
> rb_bufsz = order_base_2(ring->ring_size); diff --git
> a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 58b527a6b795..cbdc3c451bdb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1022,6 +1022,7 @@ static int vcn_v2_5_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst, bool indirect)
> volatile struct amdgpu_fw_shared *fw_shared = adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t rb_bufsz, tmp;
> + int ret;
>
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> mmUVD_POWER_STATUS), 1, @@ -1112,8 +1113,13 @@ static int
> vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
> VCN, 0, mmUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_dec;
> /* force RBC into idle state */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 9fb0d5380589..021fef318ab9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -1029,6 +1029,7 @@ static int vcn_v3_0_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst, bool indirect)
> volatile struct amdgpu_fw_shared *fw_shared = adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t rb_bufsz, tmp;
> + int ret;
>
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> mmUVD_POWER_STATUS), 1, @@ -1121,8 +1122,13 @@ static int
> vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
> WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_dec;
> /* force RBC into idle state */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index eec9133e1b2c..e8a2cb1a0c1b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1011,6 +1011,7 @@ static int vcn_v4_0_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst, bool indirect)
> volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> + int ret;
>
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> regUVD_POWER_STATUS), 1, @@ -1093,8 +1094,13 @@ static int
> vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_enc[0];
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index d8fd32c1e38e..056d9f3aa2a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -851,7 +851,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> volatile struct amdgpu_vcn4_fw_shared *fw_shared =
> adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> - int vcn_inst;
> + int vcn_inst, ret;
> uint32_t tmp;
>
> vcn_inst = GET_INST(VCN, inst_idx);
> @@ -944,8 +944,13 @@ static int vcn_v4_0_3_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> VCN, 0, regUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx,
> AMDGPU_UCODE_ID_VCN0_RAM);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx,
> AMDGPU_UCODE_ID_VCN0_RAM);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_enc[0];
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 7e37ddea6355..beade6f5be64 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -925,6 +925,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> + int ret;
>
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> regUVD_POWER_STATUS), 1, @@ -1005,8 +1006,13 @@ static int
> vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
> VCN, inst_idx, regUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_enc[0];
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 47c0bcc9e7d8..af74da292a15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -712,6 +712,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev-
> >vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> + int ret;
>
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> regUVD_POWER_STATUS), 1, @@ -765,8 +766,12 @@ static int
> vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
> VCN, inst_idx, regUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
> + dev_err(adev->dev, "%s: vcn sram load failed %d\n",
> __func__, ret);
> + if (ret)
> + return ret;
> + }
>
> ring = &adev->vcn.inst[inst_idx].ring_enc[0];
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> index cdefd7fcb0da..d8bbb9376731 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> @@ -605,7 +605,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> struct dpg_pause_state state = {.fw_based =
> VCN_DPG_STATE__PAUSE};
> - int vcn_inst;
> + int vcn_inst, ret;
> uint32_t tmp;
>
> vcn_inst = GET_INST(VCN, inst_idx);
> @@ -666,8 +666,13 @@ static int vcn_v5_0_1_start_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
> VCN, 0, regUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> - if (indirect)
> - amdgpu_vcn_psp_update_sram(adev, inst_idx,
> AMDGPU_UCODE_ID_VCN0_RAM);
> + if (indirect) {
> + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx,
> AMDGPU_UCODE_ID_VCN0_RAM);
> + if (ret) {
> + dev_err(adev->dev, "vcn sram load failed %d\n", ret);
> + return ret;
> + }
> + }
>
> /* resetting ring, fw should not check RB ring */
> fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
> --
> 2.48.1
