On Wed, Aug 20, 2025 at 7:43 AM Srinivasan Shanmugam
<srinivasan.shanmu...@amd.com> wrote:
>
> Add a new GEM domain bit AMDGPU_GEM_DOMAIN_MMIO_REMAP to allow
> userspace to request the MMIO remap (HDP flush) page via GEM_CREATE.
>
> - include/uapi/drm/amdgpu_drm.h:
> * define AMDGPU_GEM_DOMAIN_MMIO_REMAP
> * include the bit in AMDGPU_GEM_DOMAIN_MASK
>
> Cc: Christian König <christian.koe...@amd.com>
> Cc: Alex Deucher <alexander.deuc...@amd.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmu...@amd.com>
This patch should probably also add a check to
amdgpu_gem_create_ioctl() which rejects the
AMDGPU_GEM_DOMAIN_MMIO_REMAP domain for now and then drop that in your
last patch.
Alex
> ---
> include/uapi/drm/amdgpu_drm.h | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index bdedbaccf776..fc44e301adbb 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -103,6 +103,8 @@ extern "C" {
> *
> * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
> * signalling user mode queues.
> + *
> + * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for
> HDP flushing).
> */
> #define AMDGPU_GEM_DOMAIN_CPU 0x1
> #define AMDGPU_GEM_DOMAIN_GTT 0x2
> @@ -111,13 +113,15 @@ extern "C" {
> #define AMDGPU_GEM_DOMAIN_GWS 0x10
> #define AMDGPU_GEM_DOMAIN_OA 0x20
> #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
> +#define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80
> #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
> AMDGPU_GEM_DOMAIN_GTT | \
> AMDGPU_GEM_DOMAIN_VRAM | \
> AMDGPU_GEM_DOMAIN_GDS | \
> AMDGPU_GEM_DOMAIN_GWS | \
> - AMDGPU_GEM_DOMAIN_OA | \
> - AMDGPU_GEM_DOMAIN_DOORBELL)
> + AMDGPU_GEM_DOMAIN_OA | \
> + AMDGPU_GEM_DOMAIN_DOORBELL | \
> + AMDGPU_GEM_DOMAIN_MMIO_REMAP)
>
> /* Flag that CPU access will be required for the case of VRAM domain */
> #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
> --
> 2.34.1
>
