[PATCH 07/15] drm/amd/display: limit one non-related log to dGPU

[Ray Wu]

From: Charlene Liu <charlene....@amd.com>

[Why&How]
some log are for dGPU only.
Added check to limit log.

Reviewed-by: Chris Park <chris.p...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
Signed-off-by: Ray Wu <ray...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 269206ebee60..c4dd52ed377d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5622,8 +5622,8 @@ void dc_allow_idle_optimizations_internal(struct dc *dc, 
bool allow, char const
                        subvp_pipe_type[i] = 
dc_state_get_pipe_subvp_type(context, pipe);
                }
        }
-
-       DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d 
HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d 
Pipe_5=%d (caller=%s)\n",
+       if (!dc->caps.is_apu)
+               DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d 
HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d 
Pipe_5=%d (caller=%s)\n",
                        __func__, allow, idle_fclk_khz, idle_dramclk_khz, 
subvp_pipe_type[0], subvp_pipe_type[1], subvp_pipe_type[2],
                        subvp_pipe_type[3], subvp_pipe_type[4], 
subvp_pipe_type[5], caller_name);
 
-- 
2.43.0