[AMD Official Use Only - AMD Internal Distribution Only]
This serial is Reviewed-by: Sonny Jiang <sonny.ji...@amd.com>
________________________________
From: Zhang, Jesse(Jie) <jesse.zh...@amd.com>
Sent: Tuesday, September 16, 2025 11:11 PM
To: Zhang, Jesse(Jie) <jesse.zh...@amd.com>; amd-gfx@lists.freedesktop.org
<amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Koenig, Christian
<christian.koe...@amd.com>; Liu, Leo <leo....@amd.com>; Jiang, Sonny
<sonny.ji...@amd.com>; Ji, Ruili <ruili...@amd.com>
Subject: RE: [v5 1/4] drm/amdgpu: Refactor VCN v5.0.1 HW init into separate
instance function
[AMD Official Use Only - AMD Internal Distribution Only]
Ping this series.
> -----Original Message-----
> From: Jesse.Zhang <jesse.zh...@amd.com>
> Sent: Monday, September 15, 2025 10:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Koenig, Christian
> <christian.koe...@amd.com>; Liu, Leo <leo....@amd.com>; Jiang, Sonny
> <sonny.ji...@amd.com>; Zhang, Jesse(Jie) <jesse.zh...@amd.com>; Ji, Ruili
> <ruili...@amd.com>
> Subject: [v5 1/4] drm/amdgpu: Refactor VCN v5.0.1 HW init into separate
> instance
> function
>
> Split the per-instance initialization code from vcn_v5_0_1_hw_init() into a
> new
> vcn_v5_0_1_hw_init_inst() function. This improves code organization by:
>
> 1. Separating the instance-specific initialization logic 2. Making the main
> init function
> more readable 3. Following the pattern used in queue reset
>
> The SR-IOV specific initialization remains in the main function since it has
> different
> requirements.
>
> Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
> Signed-off-by: Ruili Ji <ruili...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 27 +++++++++++++++++--------
> 1 file changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> index 9c281ba6bced..3677ea9ffa43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
> @@ -253,6 +253,23 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block
> *ip_block)
> return 0;
> }
>
> +static int vcn_v5_0_1_hw_init_inst(struct amdgpu_device *adev, int i) {
> + struct amdgpu_ring *ring;
> + int vcn_inst;
> +
> + vcn_inst = GET_INST(VCN, i);
> + ring = &adev->vcn.inst[i].ring_enc[0];
> +
> + if (ring->use_doorbell)
> + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
> + ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> + 11 * vcn_inst),
> + adev->vcn.inst[i].aid_id);
> +
> + return 0;
> +}
> +
> /**
> * vcn_v5_0_1_hw_init - start and test VCN block
> *
> @@ -264,7 +281,7 @@ static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block
> *ip_block) {
> struct amdgpu_device *adev = ip_block->adev;
> struct amdgpu_ring *ring;
> - int i, r, vcn_inst;
> + int i, r;
>
> if (amdgpu_sriov_vf(adev)) {
> r = vcn_v5_0_1_start_sriov(adev);
> @@ -282,14 +299,8 @@ static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block
> *ip_block)
> if (RREG32_SOC15(VCN, GET_INST(VCN, 0),
> regVCN_RRMT_CNTL) & 0x100)
> adev->vcn.caps |=
> AMDGPU_VCN_CAPS(RRMT_ENABLED);
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - vcn_inst = GET_INST(VCN, i);
> ring = &adev->vcn.inst[i].ring_enc[0];
> -
> - if (ring->use_doorbell)
> - adev->nbio.funcs->vcn_doorbell_range(adev, ring-
> >use_doorbell,
> - ((adev->doorbell_index.vcn.vcn_ring0_1
> << 1)
> +
> - 11 * vcn_inst),
> - adev->vcn.inst[i].aid_id);
> + vcn_v5_0_1_hw_init_inst(adev, i);
>
> /* Re-init fw_shared, if required */
> vcn_v5_0_1_fw_shared_init(adev, i);
> --
> 2.49.0
