Applied. Thanks! Alex
On Tue, Oct 14, 2025 at 11:41 AM Lazar, Lijo <[email protected]> wrote: > > > > On 10/13/2025 10:00 PM, Ilya Zlobintsev wrote: > > Calling `smu_cmn_get_sysfs_buf` aligns the > > offset used by `sysfs_emit_at` to the current page boundary, which was > > previously directly returned from the various `print_clk_levels` > > implementations to be added to the buffer position. > > Instead, only the relative offset showing how much was written > > to the buffer should be returned, regardless of how it was changed > > for alignment purposes. > > > > Signed-off-by: Ilya Zlobintsev <[email protected]> > > Reviewed-by: Lijo Lazar <[email protected]> > > Thanks, > Lijo > > > --- > > .../drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 5 +++-- > > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 15 ++++++++------- > > .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 +++-- > > drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++---- > > drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 7 ++++--- > > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 ++++--- > > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 5 +++-- > > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 5 +++-- > > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++++--- > > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 ++++--- > > .../gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 5 +++-- > > .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 +++-- > > .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 7 ++++--- > > 13 files changed, 52 insertions(+), 38 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c > > index 9548bd3c624b..55401e6b2b0b 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c > > @@ -291,11 +291,12 @@ static int cyan_skillfish_print_clk_levels(struct > > smu_context *smu, > > enum smu_clk_type clk_type, > > char *buf) > > { > > - int ret = 0, size = 0; > > + int ret = 0, size = 0, start_offset = 0; > > uint32_t cur_value = 0; > > int i; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -353,7 +354,7 @@ static int cyan_skillfish_print_clk_levels(struct > > smu_context *smu, > > return ret; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > > index 0028f10ead42..bbf09aec9152 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > > @@ -1469,7 +1469,7 @@ static int navi10_print_clk_levels(struct smu_context > > *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > uint16_t *curve_settings; > > - int i, levels, size = 0, ret = 0; > > + int i, levels, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t freq_values[3] = {0}; > > uint32_t mark_index = 0; > > @@ -1484,6 +1484,7 @@ static int navi10_print_clk_levels(struct smu_context > > *smu, > > uint32_t min_value, max_value; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_GFXCLK: > > @@ -1497,11 +1498,11 @@ static int navi10_print_clk_levels(struct > > smu_context *smu, > > case SMU_DCEFCLK: > > ret = navi10_get_current_clk_freq_by_table(smu, clk_type, > > &cur_value); > > if (ret) > > - return size; > > + return size - start_offset; > > > > ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); > > if (ret) > > - return size; > > + return size - start_offset; > > > > ret = navi10_is_support_fine_grained_dpm(smu, clk_type); > > if (ret < 0) > > @@ -1511,7 +1512,7 @@ static int navi10_print_clk_levels(struct smu_context > > *smu, > > for (i = 0; i < count; i++) { > > ret = smu_v11_0_get_dpm_freq_by_index(smu, > > clk_type, i, &value); > > if (ret) > > - return size; > > + return size - start_offset; > > > > size += sysfs_emit_at(buf, size, "%d: %uMhz > > %s\n", i, value, > > cur_value == value ? "*" : > > ""); > > @@ -1519,10 +1520,10 @@ static int navi10_print_clk_levels(struct > > smu_context *smu, > > } else { > > ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, > > 0, &freq_values[0]); > > if (ret) > > - return size; > > + return size - start_offset; > > ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, > > count - 1, &freq_values[2]); > > if (ret) > > - return size; > > + return size - start_offset; > > > > freq_values[1] = cur_value; > > mark_index = cur_value == freq_values[0] ? 0 : > > @@ -1653,7 +1654,7 @@ static int navi10_print_clk_levels(struct smu_context > > *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int navi10_force_clk_levels(struct smu_context *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > > index 31c2c0386b1f..774283ac7827 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > > @@ -1281,7 +1281,7 @@ static int sienna_cichlid_print_clk_levels(struct > > smu_context *smu, > > struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; > > OverDriveTable_t *od_table = > > (OverDriveTable_t *)table_context->overdrive_table; > > - int i, size = 0, ret = 0; > > + int i, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t freq_values[3] = {0}; > > uint32_t mark_index = 0; > > @@ -1289,6 +1289,7 @@ static int sienna_cichlid_print_clk_levels(struct > > smu_context *smu, > > uint32_t min_value, max_value; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_GFXCLK: > > @@ -1434,7 +1435,7 @@ static int sienna_cichlid_print_clk_levels(struct > > smu_context *smu, > > } > > > > print_clk_out: > > - return size; > > + return size - start_offset; > > } > > > > static int sienna_cichlid_force_clk_levels(struct smu_context *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > > index 2c9869feba61..665eee58358d 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > > @@ -565,7 +565,7 @@ static int vangogh_print_legacy_clk_levels(struct > > smu_context *smu, > > DpmClocks_t *clk_table = smu->smu_table.clocks_table; > > SmuMetrics_legacy_t metrics; > > struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > bool cur_value_match_level = false; > > > > @@ -576,6 +576,7 @@ static int vangogh_print_legacy_clk_levels(struct > > smu_context *smu, > > return ret; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -658,7 +659,7 @@ static int vangogh_print_legacy_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int vangogh_print_clk_levels(struct smu_context *smu, > > @@ -666,7 +667,7 @@ static int vangogh_print_clk_levels(struct smu_context > > *smu, > > { > > DpmClocks_t *clk_table = smu->smu_table.clocks_table; > > SmuMetrics_t metrics; > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > bool cur_value_match_level = false; > > uint32_t min, max; > > @@ -678,6 +679,7 @@ static int vangogh_print_clk_levels(struct smu_context > > *smu, > > return ret; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -779,7 +781,7 @@ static int vangogh_print_clk_levels(struct smu_context > > *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int vangogh_common_print_clk_levels(struct smu_context *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > > index 3baf20f4c373..eaa9ea162f16 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > > @@ -494,7 +494,7 @@ static int > > renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) > > static int renoir_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; > > SmuMetrics_t metrics; > > bool cur_value_match_level = false; > > @@ -506,6 +506,7 @@ static int renoir_print_clk_levels(struct smu_context > > *smu, > > return ret; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_RANGE: > > @@ -550,7 +551,7 @@ static int renoir_print_clk_levels(struct smu_context > > *smu, > > size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, > > i == 2 ? "*" : ""); > > } > > - return size; > > + return size - start_offset; > > case SMU_SOCCLK: > > count = NUM_SOCCLK_DPM_LEVELS; > > cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; > > @@ -607,7 +608,7 @@ static int renoir_print_clk_levels(struct smu_context > > *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static enum amd_pm_state_type renoir_get_current_power_state(struct > > smu_context *smu) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > > index c1062e5f0393..677781060246 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > > @@ -1195,15 +1195,16 @@ static int smu_v13_0_0_print_clk_levels(struct > > smu_context *smu, > > struct smu_13_0_dpm_table *single_dpm_table; > > struct smu_13_0_pcie_table *pcie_table; > > uint32_t gen_speed, lane_width; > > - int i, curr_freq, size = 0; > > + int i, curr_freq, size = 0, start_offset = 0; > > int32_t min_value, max_value; > > int ret = 0; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > if (amdgpu_ras_intr_triggered()) { > > size += sysfs_emit_at(buf, size, "unavailable\n"); > > - return size; > > + return size - start_offset; > > } > > > > switch (clk_type) { > > @@ -1534,7 +1535,7 @@ static int smu_v13_0_0_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c > > index b081ae3e8f43..6908f9930f16 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c > > @@ -497,11 +497,12 @@ static int smu_v13_0_4_get_dpm_level_count(struct > > smu_context *smu, > > static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t min, max; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -565,7 +566,7 @@ static int smu_v13_0_4_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int smu_v13_0_4_read_sensor(struct smu_context *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c > > index f5db181ef489..4576bf008b22 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c > > @@ -861,11 +861,12 @@ static int > > smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, > > static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t min = 0, max = 0; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -928,7 +929,7 @@ static int smu_v13_0_5_print_clk_levels(struct > > smu_context *smu, > > } > > > > print_clk_out: > > - return size; > > + return size - start_offset; > > } > > > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > > index 285cf7979693..0e1b225dd875 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > > @@ -1428,7 +1428,7 @@ static int smu_v13_0_6_print_clks(struct smu_context > > *smu, char *buf, int size, > > static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type type, char *buf) > > { > > - int now, size = 0; > > + int now, size = 0, start_offset = 0; > > int ret = 0; > > struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; > > struct smu_13_0_dpm_table *single_dpm_table; > > @@ -1437,10 +1437,11 @@ static int smu_v13_0_6_print_clk_levels(struct > > smu_context *smu, > > uint32_t min_clk, max_clk; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > if (amdgpu_ras_intr_triggered()) { > > size += sysfs_emit_at(buf, size, "unavailable\n"); > > - return size; > > + return size - start_offset; > > } > > > > dpm_context = smu_dpm->dpm_context; > > @@ -1575,7 +1576,7 @@ static int smu_v13_0_6_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > > index c96fa5e49ed6..a3fc35b9011e 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > > @@ -1184,15 +1184,16 @@ static int smu_v13_0_7_print_clk_levels(struct > > smu_context *smu, > > struct smu_13_0_dpm_table *single_dpm_table; > > struct smu_13_0_pcie_table *pcie_table; > > uint32_t gen_speed, lane_width; > > - int i, curr_freq, size = 0; > > + int i, curr_freq, size = 0, start_offset = 0; > > int32_t min_value, max_value; > > int ret = 0; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > if (amdgpu_ras_intr_triggered()) { > > size += sysfs_emit_at(buf, size, "unavailable\n"); > > - return size; > > + return size - start_offset; > > } > > > > switch (clk_type) { > > @@ -1523,7 +1524,7 @@ static int smu_v13_0_7_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, > > long input) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c > > index 73b4506ef5a8..5d7e671fa3c3 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c > > @@ -1041,12 +1041,13 @@ static uint32_t > > yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu, > > static int yellow_carp_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > - int i, idx, size = 0, ret = 0; > > + int i, idx, size = 0, ret = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t min, max; > > uint32_t clk_limit = 0; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -1111,7 +1112,7 @@ static int yellow_carp_print_clk_levels(struct > > smu_context *smu, > > } > > > > print_clk_out: > > - return size; > > + return size - start_offset; > > } > > > > static int yellow_carp_force_clk_levels(struct smu_context *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > index fe00c84b1cc6..b1bd946d8e30 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > @@ -1132,11 +1132,12 @@ static int > > smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, > > static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, > > enum smu_clk_type clk_type, char *buf) > > { > > - int i, idx, ret = 0, size = 0; > > + int i, idx, ret = 0, size = 0, start_offset = 0; > > uint32_t cur_value = 0, value = 0, count = 0; > > uint32_t min, max; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > switch (clk_type) { > > case SMU_OD_SCLK: > > @@ -1202,7 +1203,7 @@ static int smu_v14_0_0_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context > > *smu, > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > > index 086501cc5213..2cea688c604f 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > > @@ -1056,15 +1056,16 @@ static int smu_v14_0_2_print_clk_levels(struct > > smu_context *smu, > > struct smu_14_0_dpm_table *single_dpm_table; > > struct smu_14_0_pcie_table *pcie_table; > > uint32_t gen_speed, lane_width; > > - int i, curr_freq, size = 0; > > + int i, curr_freq, size = 0, start_offset = 0; > > int32_t min_value, max_value; > > int ret = 0; > > > > smu_cmn_get_sysfs_buf(&buf, &size); > > + start_offset = size; > > > > if (amdgpu_ras_intr_triggered()) { > > size += sysfs_emit_at(buf, size, "unavailable\n"); > > - return size; > > + return size - start_offset; > > } > > > > switch (clk_type) { > > @@ -1374,7 +1375,7 @@ static int smu_v14_0_2_print_clk_levels(struct > > smu_context *smu, > > break; > > } > > > > - return size; > > + return size - start_offset; > > } > > > > static int smu_v14_0_2_force_clk_levels(struct smu_context *smu, >
