[AMD Official Use Only - AMD Internal Distribution Only] The series is:
Reviewed-by: Tao Zhou <[email protected]> > -----Original Message----- > From: Xie, Patrick <[email protected]> > Sent: Tuesday, November 4, 2025 2:58 PM > To: [email protected] > Cc: Zhou1, Tao <[email protected]>; Xie, Patrick <[email protected]> > Subject: [PATCH 10/10] drm/amdgpu: initialize max record count after table > reset > > initialize max record count and record offset after table reset > > Signed-off-by: Gangliang Xie <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > index 3c646d9dad77..d7e2a81bc274 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > @@ -459,6 +459,9 @@ int amdgpu_ras_eeprom_reset_table(struct > amdgpu_ras_eeprom_control *control) > hdr->tbl_size = RAS_TABLE_HEADER_SIZE + > RAS_TABLE_V2_1_INFO_SIZE; > rai->rma_status = GPU_HEALTH_USABLE; > + > + control->ras_record_offset = RAS_RECORD_START_V2_1; > + control->ras_max_record_count = > RAS_MAX_RECORD_COUNT_V2_1; > /** > * GPU health represented as a percentage. > * 0 means worst health, 100 means fully health. > @@ -469,6 +472,9 @@ int amdgpu_ras_eeprom_reset_table(struct > amdgpu_ras_eeprom_control *control) > } else { > hdr->first_rec_offset = RAS_RECORD_START; > hdr->tbl_size = RAS_TABLE_HEADER_SIZE; > + > + control->ras_record_offset = RAS_RECORD_START; > + control->ras_max_record_count = > RAS_MAX_RECORD_COUNT; > } > > csum = __calc_hdr_byte_sum(control); > -- > 2.34.1
