Trivial compaction of some repetitive code: add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-216 (-216) Function old new delta gfx_v10_0_read_wave_data 580 364 -216 Total: Before=8979233, After=8979017, chg -0.00%
Signed-off-by: Tvrtko Ursulin <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 38 ++++++++++++++------------ 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 4999e57a11df..0ff7a4e1a449 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4497,6 +4497,8 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* in gfx10 the SIMD_ID is specified as part of the INSTANCE * field when performing a select_se_sh so it should be * zero here @@ -4504,23 +4506,25 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id WARN_ON(simd != 0); /* type 2 wave data */ - dst[(*no_fields)++] = 2; - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + *dst++ = 2; + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, -- 2.48.0
