> -----Original Message-----
> From: Borah, Chaitanya Kumar <[email protected]>
> Sent: Friday, December 19, 2025 12:26 PM
> To: [email protected]; [email protected]; intel-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Shankar, Uma
> <[email protected]>; Kandpal, Suraj <[email protected]>;
> [email protected]; [email protected]; Roper, Matthew D
> <[email protected]>
> Subject: [PATCH 01/13] drm/i915/color: Place 3D LUT after CSC in plane color
> pipeline
>
> Commit 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline")
> introduced
> the 3D LUT block before the CSC stage. This ordering is incorrect.
>
> Move the 3D LUT block to its correct position in the plane color
> pipeline:
>
> [Pre-CSC] -> [CSC] -> [3DLUT] -> [Post-CSC]
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline")
> Signed-off-by: Chaitanya Kumar Borah <[email protected]>
> ---
> .../drm/i915/display/intel_color_pipeline.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 942d9b9c93ce..684641c8323b 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -39,6 +39,15 @@ int _intel_color_pipeline_plane_init(struct drm_plane
> *plane, struct drm_prop_en
> /* TODO: handle failures and clean up */
> prev_op = &colorop->base;
>
> + colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> + ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
> +
> DRM_COLOROP_FLAG_ALLOW_BYPASS);
> + if (ret)
> + return ret;
> +
> + drm_colorop_set_next_property(prev_op, &colorop->base);
> + prev_op = &colorop->base;
> +
> if (DISPLAY_VER(display) >= 35 &&
> intel_color_crtc_has_3dlut(display, pipe) &&
> plane->type == DRM_PLANE_TYPE_PRIMARY) { @@ -55,15 +64,6
> @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct
> drm_prop_en
> prev_op = &colorop->base;
> }
>
> - colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
> - ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
> -
> DRM_COLOROP_FLAG_ALLOW_BYPASS);
> - if (ret)
> - return ret;
> -
> - drm_colorop_set_next_property(prev_op, &colorop->base);
> - prev_op = &colorop->base;
> -
> colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
> ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
> PLANE_GAMMA_SIZE,
> --
> 2.25.1
