Ping on this series. Alex
On Mon, Jan 12, 2026 at 10:21 AM Alex Deucher <[email protected]> wrote: > > The first change prevents the hw from overwriting the ring with > NOOPs after a reset. This is helpful for debugging user queues > since the contents will be retained. The second change disables > conversion of XNACK to XACK during a queue reset. > > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > index 624929473b136..6145cfc0334b2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > @@ -3616,14 +3616,24 @@ static int gfx_v11_0_cp_gfx_start(struct > amdgpu_device *adev) > struct amdgpu_ring *ring; > const struct cs_section_def *sect = NULL; > const struct cs_extent_def *ext = NULL; > - int r, i; > int ctx_reg_offset; > + int r, i; > + u32 val; > > /* init the CP */ > WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, > adev->gfx.config.max_hw_contexts - 1); > WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); > > + if (!amdgpu_sriov_vf(adev)) { > + val = RREG32_SOC15(GC, 0, regCP_DEBUG_2); > + val = REG_SET_FIELD(val, CP_DEBUG_2, > RB_PACKET_INJECTOR_DISABLE, 1); > + WREG32_SOC15(GC, 0, regCP_DEBUG_2, val); > + val = RREG32_SOC15(GC, 0, regCPF_UTCL1_CNTL); > + val = REG_SET_FIELD(val, CPF_UTCL1_CNTL, VMID_RESET_MODE, 1); > + WREG32_SOC15(GC, 0, regCPF_UTCL1_CNTL, val); > + } > + > if (!amdgpu_async_gfx_ring) > gfx_v11_0_cp_gfx_enable(adev, true); > > -- > 2.52.0 >
