On Tue, Feb 3, 2026 at 11:44 PM Pratik Vishwakarma <[email protected]> wrote: > > Some SMU messages have changed to multi reg read/write > Initialize during smu_early_init > > Signed-off-by: Pratik Vishwakarma <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c > index c3f22844ba2f..d58b0bc2bf78 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c > @@ -52,6 +52,12 @@ > #define mmMP1_SMN_C2PMSG_32 0x0060 > #define mmMP1_SMN_C2PMSG_32_BASE_IDX 1 > > +#define mmMP1_SMN_C2PMSG_33 0x0061 > +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1 > + > +#define mmMP1_SMN_C2PMSG_34 0x0062 > +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1 > + > /* MALLPowerController message arguments (Defines for the Cache mode > control) */ > #define SMU_MALL_PMFW_CONTROL 0 > #define SMU_MALL_DRIVER_CONTROL 1 > @@ -1347,7 +1353,9 @@ static void smu_v15_0_0_init_msg_ctl(struct smu_context > *smu) > ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30); > ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31); > ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, > mmMP1_SMN_C2PMSG_32); > - ctl->config.num_arg_regs = 1; > + ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, > mmMP1_SMN_C2PMSG_33); > + ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, > mmMP1_SMN_C2PMSG_34); > + ctl->config.num_arg_regs = 3; > ctl->ops = &smu_msg_v1_ops; > ctl->default_timeout = adev->usec_timeout * 20; > ctl->message_map = smu_v15_0_0_message_map; > -- > 2.43.0 >
