From: Saleemkhan Jamadar <[email protected]> Add mqd configuration for VCN IP. Update the UMSCH interface w.r.t FW change.
Signed-off-by: Saleemkhan Jamadar <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h | 16 +++++++++------- drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 4 ++-- .../gpu/drm/amd/include/umsch_mm_4_0_api_def.h | 12 +++++------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h index 2c771a753778..af34faa5e1ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h @@ -26,10 +26,8 @@ #define __AMDGPU_UMSCH_MM_H__ enum UMSCH_SWIP_ENGINE_TYPE { - UMSCH_SWIP_ENGINE_TYPE_VCN0 = 0, - UMSCH_SWIP_ENGINE_TYPE_VCN1 = 1, - UMSCH_SWIP_ENGINE_TYPE_VCN = 2, - UMSCH_SWIP_ENGINE_TYPE_VPE = 3, + UMSCH_SWIP_ENGINE_TYPE_VCN = 0, + UMSCH_SWIP_ENGINE_TYPE_VPE = 1, UMSCH_SWIP_ENGINE_TYPE_MAX }; @@ -92,8 +90,10 @@ struct umsch_mm_add_queue_input { struct { uint32_t is_context_suspended : 1; uint32_t collaboration_mode : 1; - uint32_t reserved : 30; + uint32_t mqd_type : 2; + uint32_t reserved : 28; }; + u64 fence_signal_addr; }; struct umsch_mm_remove_queue_input { @@ -107,8 +107,10 @@ struct MQD_INFO { uint32_t rb_base_hi; uint32_t rb_base_lo; uint32_t rb_size; - uint32_t wptr_val; - uint32_t rptr_val; + u32 wptr_addr_monotonic_hi; + u32 wptr_addr_monotonic_lo; + u32 rptr_addr_monotonic_hi; + u32 rptr_addr_monotonic_lo; uint32_t unmapped; uint32_t vmid; }; diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c index ce3bb12e3572..79e1ec9933c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c @@ -282,8 +282,6 @@ static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch) adev->vpe.collaborate_mode ? 0x3 : 0x0; set_hw_resources.engine_mask = umsch->engine_mask; - set_hw_resources.vcn0_hqd_mask[0] = umsch->vcn0_hqd_mask; - set_hw_resources.vcn1_hqd_mask[0] = umsch->vcn1_hqd_mask; set_hw_resources.vcn_hqd_mask[0] = umsch->vcn_hqd_mask[0]; set_hw_resources.vcn_hqd_mask[1] = umsch->vcn_hqd_mask[1]; set_hw_resources.vpe_hqd_mask[0] = umsch->vpe_hqd_mask; @@ -356,6 +354,8 @@ static int umsch_mm_v4_0_add_queue(struct amdgpu_umsch_mm *umsch, add_queue.vm_context_cntl = input_ptr->vm_context_cntl; add_queue.is_context_suspended = input_ptr->is_context_suspended; add_queue.collaboration_mode = adev->vpe.collaborate_mode ? 1 : 0; + add_queue.mqd_type = input_ptr->mqd_type; + add_queue.fence_signal_addr = input_ptr->fence_signal_addr; add_queue.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr; add_queue.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq; diff --git a/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h b/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h index ca83e9e5c3ff..735ec05859fe 100644 --- a/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h +++ b/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h @@ -159,10 +159,8 @@ enum UMSCH_AMD_PRIORITY_LEVEL { }; enum UMSCH_ENGINE_TYPE { - UMSCH_ENGINE_TYPE_VCN0 = 0, - UMSCH_ENGINE_TYPE_VCN1 = 1, - UMSCH_ENGINE_TYPE_VCN = 2, - UMSCH_ENGINE_TYPE_VPE = 3, + UMSCH_ENGINE_TYPE_VCN = 0, + UMSCH_ENGINE_TYPE_VPE = 1, UMSCH_ENGINE_TYPE_MAX }; @@ -215,8 +213,6 @@ union UMSCHAPI__SET_HW_RESOURCES { uint32_t collaboration_mask_vpe; uint32_t engine_mask; uint32_t logging_vmid; - uint32_t vcn0_hqd_mask[MAX_VCN0_INSTANCES]; - uint32_t vcn1_hqd_mask[MAX_VCN1_INSTANCES]; uint32_t vcn_hqd_mask[MAX_VCN_INSTANCES]; uint32_t vpe_hqd_mask[MAX_VPE_INSTANCES]; uint64_t g_sch_ctx_gpu_mc_ptr; @@ -299,11 +295,13 @@ union UMSCHAPI__ADD_QUEUE { struct { uint32_t is_context_suspended : 1; uint32_t collaboration_mode : 1; - uint32_t reserved : 30; + uint32_t mqd_type : 2; + uint32_t reserved : 28; }; struct UMSCH_API_STATUS api_status; uint32_t process_csa_array_index; uint32_t context_csa_array_index; + u64 fence_signal_addr; }; uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; -- 2.43.0
