On 2026. január 28., szerda 2:51:38 közép-európai téli idő Wayne Lin wrote:
> From: Nicholas Carbones <[email protected]>
>
> [Why]
> Post-driver cases always use linear tiling yet there is no dedicated
> Gfx handling for this condition.
>
> [How]
> Add DcGfxBase/DalGfxBase to gfx version enums and set tiling to linear
> when it is used. Also, enforce the use of proper tiling format as tiling
> information is used.
>
> Reviewed-by: Dillon Varone <[email protected]>
> Signed-off-by: Nicholas Carbones <[email protected]>
> Signed-off-by: Wayne Lin <[email protected]>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
> drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 7 +++++++
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ++-
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 +++
> drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 +++
> drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 +
> drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 2 ++
> drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c | 2 ++
> drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c | 2 ++
> drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 7 ++++++-
> .../amd/display/dc/resource/dcn32/dcn32_resource_helpers.c | 3 ++-
> 13 files changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index
> fcc48994c3e3..333ff8557732 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -8033,6 +8033,7 @@ static enum dc_status
> dm_validate_stream_and_context(struct dc *dc,
> dc_plane_state->plane_size.chroma_size.height = stream->src.height;
> dc_plane_state->plane_size.chroma_size.width = stream->src.width;
> dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
> + dc_plane_state->tiling_info.gfxversion = DcGfxVersion9;
> dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
> dc_plane_state->rotation = ROTATION_ANGLE_0;
> dc_plane_state->is_tiling_rotated = false;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4305691ba45e..441b7e0a3b22
> 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2768,6 +2768,7 @@ static struct surface_update_descriptor
> get_plane_info_update_type(const struct case DcGfxVersion7:
> case DcGfxVersion8:
> case DcGfxVersionUnknown:
> + case DcGfxBase:
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index
> 052d573408c3..a13d9d7dd6c5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> @@ -2065,6 +2065,13 @@ void get_surface_tile_visual_confirm_color(
> while (bottom_pipe_ctx->bottom_pipe != NULL)
> bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
>
> + if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion ==
DcGfxBase) {
> + /* LINEAR Surface - set border color to red */
> + color->color_r_cr = color_value;
> + return;
> + }
> +
> + ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion ==
> DcGfxVersion9); switch
> (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { case
> DC_SW_LINEAR:
> /* LINEAR Surface - set border color to red */
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index
> 848c267ef11e..b4e5a79e9749 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -4434,6 +4434,7 @@ enum dc_status dc_validate_global_state(
>
> if (dc->res_pool->funcs-
>patch_unknown_plane_state &&
> pipe_ctx->plane_state
&&
> + pipe_ctx->plane_state-
>tiling_info.gfxversion == DcGfxVersion9 &&
> pipe_ctx->plane_state-
>tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
> result =
> dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); if
> (result != DC_OK)
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index
> cfa569a7bff1..7121629da38e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> @@ -342,7 +342,8 @@ enum swizzle_mode_addr3_values {
> };
>
> enum dc_gfxversion {
> - DcGfxVersion7 = 0,
> + DcGfxBase = 0,
> + DcGfxVersion7,
> DcGfxVersion8,
> DcGfxVersion9,
> DcGfxVersion10,
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index
> 1c2009e38aa1..5df58fadc862 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
> @@ -100,6 +100,7 @@ static enum mi_bits_per_pixel get_mi_bpp(
> static enum mi_tiling_format get_mi_tiling(
> struct dc_tiling_info *tiling_info)
> {
> + ASSERT(tiling_info->gfxversion == DcGfxVersion8);
> switch (tiling_info->gfx8.array_mode) {
> case DC_ARRAY_1D_TILED_THIN1:
> case DC_ARRAY_1D_TILED_THICK:
> @@ -433,6 +434,7 @@ static void program_tiling(
> struct dce_mem_input *dce_mi, const struct dc_tiling_info *info)
> {
> if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
> + ASSERT(info->gfxversion == DcGfxVersion9);
> REG_UPDATE_6(GRPH_CONTROL,
> GRPH_SW_MODE, info->gfx9.swizzle,
> GRPH_NUM_BANKS, log_2(info-
>gfx9.num_banks),
> @@ -447,6 +449,7 @@ static void program_tiling(
> }
>
> if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */
> + ASSERT(info->gfxversion == DcGfxVersion8);
Hi,
GFX7 hits this assertion. Assuming that GFX7 requires the same register
programming as GFX8, the assertion should be changed to:
ASSERT(info->gfxversion == DcGfxVersion7 ||
info->gfxversion == DcGfxVersion8);
That being said, I don't see much value in these assertions, because the
"dce_mi->masks->GRPH_MICRO_TILE_MODE" check already implies that the code is
running on a GFX version that has this register.
Best regards,
Timur
> REG_UPDATE_9(GRPH_CONTROL,
> GRPH_NUM_BANKS, info-
>gfx8.num_banks,
> GRPH_BANK_WIDTH, info-
>gfx8.bank_width,
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index
> 2c43c2422638..67cfca3361fb 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
> @@ -165,6 +165,8 @@ static void program_tiling(
> const struct dc_tiling_info *info,
> const enum surface_pixel_format pixel_format)
> {
> + ASSERT(info->gfxversion == DcGfxVersion8);
> +
> uint32_t value = 0;
>
> set_reg_field_value(value, info->gfx8.num_banks,
> @@ -541,6 +543,7 @@ static const unsigned int *get_dvmm_hw_setting(
> else
> bpp = bpp_8;
>
> + ASSERT(tiling_info->gfxversion == DcGfxVersion8);
> switch (tiling_info->gfx8.array_mode) {
> case DC_ARRAY_1D_TILED_THIN1:
> case DC_ARRAY_1D_TILED_THICK:
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index
> 74962791302f..71eeee02c0fa 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
> @@ -1006,6 +1006,7 @@ bool dcn_validate_bandwidth(
>
> v->source_pixel_format[input_idx] =
tl_pixel_format_to_bw_defs(
> pipe->plane_state-
>format);
> + ASSERT(pipe->plane_state-
>tiling_info.gfxversion == DcGfxVersion9);
> v->source_surface_mode[input_idx] =
tl_sw_mode_to_bw_defs(
> pipe->plane_state-
>tiling_info.gfx9.swizzle);
> v->lb_bit_per_pixel[input_idx] =
> tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); diff --git
> a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
> b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index
> 6378e3fd7249..e697d9bf1b44 100644
> --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
> @@ -145,6 +145,8 @@ void hubp1_program_tiling(
> {
> struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
>
> + ASSERT(info->gfxversion == DcGfxVersion9);
> +
> REG_UPDATE_6(DCSURF_ADDR_CONFIG,
> NUM_PIPES, log_2(info->gfx9.num_pipes),
> NUM_BANKS, log_2(info->gfx9.num_banks),
> diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
> b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index
> 92288de4cc10..4715e60e812a 100644
> --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
> @@ -313,6 +313,8 @@ static void hubp2_program_tiling(
> const struct dc_tiling_info *info,
> const enum surface_pixel_format pixel_format)
> {
> + ASSERT(info->gfxversion == DcGfxVersion9);
> +
> REG_UPDATE_3(DCSURF_ADDR_CONFIG,
> NUM_PIPES, log_2(info->gfx9.num_pipes),
> PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
> diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
> b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index
> 0cc6f4558989..207c2f86b7d7 100644
> --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
> @@ -321,6 +321,8 @@ void hubp3_program_tiling(
> const struct dc_tiling_info *info,
> const enum surface_pixel_format pixel_format)
> {
> + ASSERT(info->gfxversion == DcGfxVersion9);
> +
> REG_UPDATE_4(DCSURF_ADDR_CONFIG,
> NUM_PIPES, log_2(info->gfx9.num_pipes),
> PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
> diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
> b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index
> c205500290ec..861e940250af 100644
> --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
> @@ -589,7 +589,12 @@ void hubp401_program_tiling(
> *
> * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D
dimension)
> which is HW default. */
> - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info-
>gfx_addr3.swizzle);
> + if (info->gfxversion == DcGfxAddr3) {
> + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info-
>gfx_addr3.swizzle);
> + } else {
> + /* linear */
> + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, 0);
> + }
> }
>
> void hubp401_program_size(
> diff --git
> a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
> b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
> index f5a4e97c40ce..7d99f5d79e6d 100644
> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
> +++
> b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@
> -401,7 +401,8 @@ void dcn32_set_det_allocations(struct dc *dc, struct
> dc_state *context, */
> if (pipe_cnt == 1) {
> pipes[0].pipe.src.det_size_override =
DCN3_2_MAX_DET_SIZE;
> - if (pipe->plane_state && !disable_unbounded_requesting
&&
> pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { +
if
> (pipe->plane_state && !disable_unbounded_requesting &&
> pipe->plane_state->tiling_info.gfxversion != DcGfxBase &&
> + !(pipe->plane_state->tiling_info.gfxversion
== DcGfxVersion9 &&
> pipe->plane_state->tiling_info.gfx9.swizzle == DC_SW_LINEAR)) { if
> (!is_dual_plane(pipe->plane_state->format)) {
>
pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
>
pipes[0].pipe.src.unbounded_req_mode = true;
