From: decce6 <[email protected]> [ Upstream commit 49fe2c57bdc0acff9d2551ae337270b6fd8119d9 ]
This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from 850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This patch is for amdgpu. Signed-off-by: decce6 <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Sasha Levin <[email protected]> --- LLM Generated explanations, may be completely bogus: ## Analysis ### What the commit does This adds a hardware-specific clock speed limitation (quirk) for the AMD Radeon R5 M420 GPU (PCI device 0x666f, revision 0x00, HAINAN chip family). It caps the core clock at 800 MHz and memory clock at 950 MHz, down from 850/1000 MHz defaults, to fix GPU instability. ### Classification: Hardware Quirk/Workaround This falls squarely into the **hardware quirk** exception category for stable backports. The change: 1. **Is small and contained**: Only 5 lines added to a single file 2. **Follows an established pattern exactly**: The existing function `si_apply_state_adjust_rules()` already contains identical quirks for other HAINAN and OLAND device/revision combinations (lines 3454-3481). The new code is a copy of this pattern. 3. **Fixes a real stability issue**: Without the clock cap, this specific GPU is unstable at default clocks. This means crashes, display corruption, or hangs for users with this hardware. 4. **Has zero risk to other hardware**: The change is gated by `adev->pdev->device == 0x666f && adev->pdev->revision == 0x00`, so it only affects one specific GPU variant. 5. **No new features or APIs**: Just limiting existing clock values. ### Risk Assessment **Very low risk.** The change: - Adds a device-specific conditional inside existing well-tested infrastructure - Cannot affect any other device (specific PCI device ID + revision check) - The `max_sclk`/`max_mclk` capping mechanism is already used by multiple other entries (lines 3575-3581) - Was reviewed and signed off by Alex Deucher, the AMD GPU maintainer ### User Impact Users with the AMD Radeon R5 M420 (a budget laptop GPU) experience instability without this fix. This is found in many budget laptops and the fix makes the difference between a working and non-working GPU under the amdgpu driver. ### Dependency Check No dependencies. The code being modified (`si_apply_state_adjust_rules` with HAINAN device checks) has been present in the kernel for years (since the amdgpu SI support was added). The `CHIP_HAINAN` branch and the `max_sclk`/`max_mclk` mechanism are well-established in all stable trees that support this hardware. ### Verification - Read the diff and confirmed it adds exactly 5 lines matching the existing quirk pattern in `si_apply_state_adjust_rules()` (lines 3454-3466 for existing HAINAN quirks) - Verified `max_sclk` and `max_mclk` are used at lines 3575-3581 to cap performance levels - confirming the mechanism works - Confirmed the change is authored by an external contributor and signed off by Alex Deucher (AMD GPU subsystem maintainer) - Confirmed via `git log` that `si_dpm.c` has a history of receiving similar quirk/workaround fixes (e.g., "Workaround SI powertune issue on Radeon 430") - lore.kernel.org search confirmed the patch went through multiple review iterations (Jan-Feb 2026) before being accepted by AMD maintainer - Could NOT verify exact stable tree versions containing the base HAINAN support, but CHIP_HAINAN support in amdgpu has existed since at least v4.x (unverified exact version) ### Conclusion This is a textbook hardware quirk addition - small, safe, device- specific, zero risk to other hardware, fixes a real stability issue for users with this GPU. It follows the exact same pattern as existing entries in the same function. This is exactly the type of change that stable trees exist to deliver. **YES** drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 695432d3045ff..2d8d86efe2e73 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3464,6 +3464,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, max_sclk = 60000; max_mclk = 80000; } + if ((adev->pdev->device == 0x666f) && + (adev->pdev->revision == 0x00)) { + max_sclk = 80000; + max_mclk = 95000; + } } else if (adev->asic_type == CHIP_OLAND) { if ((adev->pdev->revision == 0xC7) || (adev->pdev->revision == 0x80) || -- 2.51.0
