On Wed, Feb 25, 2026 at 4:54 AM sguttula <[email protected]> wrote: > > This change will update GFX to ASP mailbox registers to AXI > address space macros instead of SMN address space. > > This will help to fix PSP TOC load failure during secureboot. > PSP allowed RSMU security policy for R/W on AXI address space not > for SMN address space, GFX Driver Need to use AXI address reg. > > Signed-off-by: sguttula <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/psp_v15_0.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c > b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c > index 723ddae17644..73a709773e85 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c > @@ -69,12 +69,12 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp, > 0x80000000, 0x80000000, false); > } else { > /* Write the ring destroy command*/ > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, > GFX_CTRL_CMD_ID_DESTROY_RINGS); > /* there might be handshake issue with hardware which needs > delay */ > mdelay(20); > /* Wait for response flag (bit 31) */ > - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_SMN_C2PMSG_64), > + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_PCRU1_MPASP_C2PMSG_64), > 0x80000000, 0x80000000, false); > } > > @@ -116,7 +116,7 @@ static int psp_v15_0_0_ring_create(struct psp_context > *psp, > > } else { > /* Wait for sOS ready for ring creation */ > - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_SMN_C2PMSG_64), > + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_PCRU1_MPASP_C2PMSG_64), > 0x80000000, 0x80000000, false); > if (ret) { > DRM_ERROR("Failed to wait for trust OS ready for ring > creation\n"); > @@ -125,23 +125,23 @@ static int psp_v15_0_0_ring_create(struct psp_context > *psp, > > /* Write low address of the ring to C2PMSG_69 */ > psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, > psp_ring_reg); > /* Write high address of the ring to C2PMSG_70 */ > psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, > psp_ring_reg); > /* Write size of ring to C2PMSG_71 */ > psp_ring_reg = ring->ring_size; > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, > psp_ring_reg); > /* Write the ring initialization command to C2PMSG_64 */ > psp_ring_reg = ring_type; > psp_ring_reg = psp_ring_reg << 16; > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, > psp_ring_reg); > > /* there might be handshake issue with hardware which needs > delay */ > mdelay(20); > > /* Wait for response flag (bit 31) in C2PMSG_64 */ > - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_SMN_C2PMSG_64), > + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > regMPASP_PCRU1_MPASP_C2PMSG_64), > 0x80000000, 0x8000FFFF, false); > } > > @@ -174,7 +174,7 @@ static uint32_t psp_v15_0_0_ring_get_wptr(struct > psp_context *psp) > if (amdgpu_sriov_vf(adev)) > data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); > else > - data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); > + data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); > > return data; > } > @@ -188,7 +188,7 @@ static void psp_v15_0_0_ring_set_wptr(struct psp_context > *psp, uint32_t value) > WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, > GFX_CTRL_CMD_ID_CONSUME_CMD); > } else > - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); > + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); > } > > static const struct psp_funcs psp_v15_0_0_funcs = { > -- > 2.43.0 >
