On Wed, Mar 18, 2026 at 7:22 AM Stanley.Yang <[email protected]> wrote:
>
> Add amdgpu_regs_pcie64 debugfs node to
> read/write 64bit PCIE registers.
>
> Signed-off-by: Stanley.Yang <[email protected]>

Acked-by: Alex Deucher <[email protected]>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 113 ++++++++++++++++++++
>  1 file changed, 113 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> index 6fdcd9c78324..e15b3aa02919 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> @@ -622,6 +622,111 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct 
> file *f, const char __user
>         amdgpu_virt_disable_access_debugfs(adev);
>         return r;
>  }
> +/**
> + * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register
> + *
> + * @f: open file handle
> + * @buf: User buffer to store read data in
> + * @size: Number of bytes to read
> + * @pos:  Offset to seek to
> + */
> +static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user 
> *buf,
> +                    size_t size, loff_t *pos)
> +{
> +       struct amdgpu_device *adev = file_inode(f)->i_private;
> +       ssize_t result = 0;
> +       int r;
> +
> +       if (size & 0x7 || *pos & 0x7)
> +               return -EINVAL;
> +
> +       r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> +       if (r < 0) {
> +               pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +               return r;
> +       }
> +
> +       r = amdgpu_virt_enable_access_debugfs(adev);
> +       if (r < 0) {
> +               pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +               return r;
> +       }
> +
> +       while (size) {
> +               uint64_t value;
> +
> +               value = RREG64_PCIE_EXT(*pos);
> +
> +               r = put_user(value, (uint64_t *)buf);
> +               if (r)
> +                       goto out;
> +
> +               result += 8;
> +               buf += 8;
> +               *pos += 8;
> +               size -= 8;
> +       }
> +
> +       r = result;
> +out:
> +       pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
> +       pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +       amdgpu_virt_disable_access_debugfs(adev);
> +       return r;
> +}
> +
> +/**
> + * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register
> + *
> + * @f: open file handle
> + * @buf: User buffer to write data from
> + * @size: Number of bytes to write
> + * @pos:  Offset to seek to
> + */
> +static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char 
> __user *buf,
> +                     size_t size, loff_t *pos)
> +{
> +       struct amdgpu_device *adev = file_inode(f)->i_private;
> +       ssize_t result = 0;
> +       int r;
> +
> +       if (size & 0x7 || *pos & 0x7)
> +               return -EINVAL;
> +
> +       r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> +       if (r < 0) {
> +               pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +               return r;
> +       }
> +
> +       r = amdgpu_virt_enable_access_debugfs(adev);
> +       if (r < 0) {
> +               pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +               return r;
> +       }
> +
> +       while (size) {
> +               uint64_t value;
> +
> +               r = get_user(value, (uint64_t *)buf);
> +               if (r)
> +                       goto out;
> +
> +               WREG64_PCIE_EXT(*pos, value);
> +
> +               result += 8;
> +               buf += 8;
> +               *pos += 8;
> +               size -= 8;
> +       }
> +
> +       r = result;
> +out:
> +       pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
> +       pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> +       amdgpu_virt_disable_access_debugfs(adev);
> +       return r;
> +}
>
>  /**
>   * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
> @@ -1544,6 +1649,12 @@ static const struct file_operations 
> amdgpu_debugfs_regs_pcie_fops = {
>         .write = amdgpu_debugfs_regs_pcie_write,
>         .llseek = default_llseek
>  };
> +static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = {
> +       .owner = THIS_MODULE,
> +       .read = amdgpu_debugfs_regs_pcie64_read,
> +       .write = amdgpu_debugfs_regs_pcie64_write,
> +       .llseek = default_llseek
> +};
>  static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
>         .owner = THIS_MODULE,
>         .read = amdgpu_debugfs_regs_smc_read,
> @@ -1606,6 +1717,7 @@ static const struct file_operations *debugfs_regs[] = {
>         &amdgpu_debugfs_gprwave_fops,
>         &amdgpu_debugfs_regs_didt_fops,
>         &amdgpu_debugfs_regs_pcie_fops,
> +       &amdgpu_debugfs_regs_pcie64_fops,
>         &amdgpu_debugfs_regs_smc_fops,
>         &amdgpu_debugfs_gca_config_fops,
>         &amdgpu_debugfs_sensors_fops,
> @@ -1623,6 +1735,7 @@ static const char * const debugfs_regs_names[] = {
>         "amdgpu_gprwave",
>         "amdgpu_regs_didt",
>         "amdgpu_regs_pcie",
> +       "amdgpu_regs_pcie64",
>         "amdgpu_regs_smc",
>         "amdgpu_gca_config",
>         "amdgpu_sensors",
> --
> 2.25.1
>

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