From: Jerry Zuo <jerry....@amd.com>
Allocate memory for the second pipe allocate_mem_input() needs to
be done prior to program pipe front end. It shows sensitive to
Fiji. Failure to do so will cause error in allocate memory
allocate_mem_input() on the second connected display.
Signed-off-by: Jerry Zuo <jerry....@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang....@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Reviewed-by: Harry Wentland <harry.wentl...@amd.com>
---
.../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 73072650530c..df6da5428e74 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1377,16 +1377,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
program_scaler(dc, pipe_ctx);
}
- /* mst support - use total stream count */
- if (pipe_ctx->plane_res.mi != NULL) {
- pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
- pipe_ctx->plane_res.mi,
- stream->timing.h_total,
- stream->timing.v_total,
- stream->timing.pix_clk_khz,
- context->stream_count);
- }
-
pipe_ctx->stream->sink->link->psr_enabled = false;
return DC_OK;
@@ -2904,6 +2894,15 @@ static void dce110_apply_ctx_for_surface(
if (pipe_ctx->stream != stream)
continue;
+ /* Need to allocate mem before program front end for Fiji */
+ if (pipe_ctx->plane_res.mi != NULL)
+ pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
+ pipe_ctx->plane_res.mi,
+ pipe_ctx->stream->timing.h_total,
+ pipe_ctx->stream->timing.v_total,
+ pipe_ctx->stream->timing.pix_clk_khz,
+ context->stream_count);
+
dce110_program_front_end_for_pipe(dc, pipe_ctx);
program_surface_visibility(dc, pipe_ctx);
--
2.14.1
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