On Tue, Mar 31, 2026 at 9:41 AM Ramalingeswara Reddy, Kanala <[email protected]> wrote: > > Define and use regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 and > regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 for TSC upper and lower count. > > Signed-off-by: Ramalingeswara Reddy, Kanala > <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 31 +++++++++++++++++++++----- > 1 file changed, 26 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > index ae39b9e1f7d6..a40479fb00f9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > @@ -64,6 +64,11 @@ > #define regPC_CONFIG_CNTL_1 0x194d > #define regPC_CONFIG_CNTL_1_BASE_IDX 1 > > +#define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 0x0030 > +#define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0_BASE_IDX 1 > +#define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 0x0031 > +#define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0_BASE_IDX 1 > + > #define regCP_GFX_MQD_CONTROL_DEFAULT > 0x00000100 > #define regCP_GFX_HQD_VMID_DEFAULT > 0x00000000 > #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT > 0x00000000 > @@ -5234,11 +5239,27 @@ static uint64_t > gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) > amdgpu_gfx_off_ctrl(adev, true); > } else { > preempt_disable(); > - clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, > regGOLDEN_TSC_COUNT_UPPER); > - clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, > regGOLDEN_TSC_COUNT_LOWER); > - clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, > regGOLDEN_TSC_COUNT_UPPER); > - if (clock_counter_hi_pre != clock_counter_hi_after) > - clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, > regGOLDEN_TSC_COUNT_LOWER); > + if (amdgpu_ip_version(adev, SMUIO_HWIP, 0) < IP_VERSION(15, > 0, 0)) { > + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, > 0, > + regGOLDEN_TSC_COUNT_UPPER); > + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, > + regGOLDEN_TSC_COUNT_LOWER); > + clock_counter_hi_after = > (uint64_t)RREG32_SOC15(SMUIO, 0, > + regGOLDEN_TSC_COUNT_UPPER); > + if (clock_counter_hi_pre != clock_counter_hi_after) > + clock_counter_lo = > (uint64_t)RREG32_SOC15(SMUIO, 0, > + regGOLDEN_TSC_COUNT_LOWER); > + } else { > + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, > 0, > + regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); > + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, > + regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); > + clock_counter_hi_after = > (uint64_t)RREG32_SOC15(SMUIO, 0, > + regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); > + if (clock_counter_hi_pre != clock_counter_hi_after) > + clock_counter_lo = > (uint64_t)RREG32_SOC15(SMUIO, 0, > + > regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); > + } > preempt_enable(); > } > clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); > -- > 2.53.0 >
