On Fri, May 8, 2026 at 3:49 AM Jesse Zhang <[email protected]> wrote: > > gfx_v12_0_init_microcode() always loads RS64 CP ucode but never set > adev->gfx.rs64_enable, so it stayed false and code that branches on it > (e.g. MEC pipe reset) used the legacy CP_MEC_CNTL path incorrectly. > > Match GFX11: derive RS64 mode from the PFP firmware header (v2.0) via > amdgpu_ucode_hdr_version(). Log at debug when RS64 is enabled. > > Signed-off-by: Jesse Zhang <[email protected]>
This can land right away. Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > index b866a944f878..f47928dcd848 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > @@ -602,6 +602,13 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device > *adev) > "amdgpu/%s_pfp.bin", ucode_prefix); > if (err) > goto out; > + > + adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( > + (union amdgpu_firmware_header *) > + adev->gfx.pfp_fw->data, 2, 0); > + if (adev->gfx.rs64_enable) > + dev_dbg(adev->dev, "CP RS64 enable\n"); > + > amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); > amdgpu_gfx_cp_init_microcode(adev, > AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); > > -- > 2.49.0 >
