---
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 9 --------
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 3 ---
.../amd/display/dc/hwss/dcn30/dcn30_init.c | 1 -
.../amd/display/dc/hwss/dcn31/dcn31_init.c | 1 -
.../amd/display/dc/hwss/dcn314/dcn314_init.c | 1 -
.../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 -
.../amd/display/dc/hwss/dcn35/dcn35_init.c | 1 -
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 -
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 -
.../amd/display/dc/hwss/dcn42/dcn42_init.c | 1 -
.../drm/amd/display/dc/hwss/hw_sequencer.h | 3 ---
.../amd/display/dc/inc/hw/timing_generator.h | 1 -
.../amd/display/dc/optc/dcn30/dcn30_optc.c | 22 -------------------
.../amd/display/dc/optc/dcn30/dcn30_optc.h | 1 -
.../amd/display/dc/optc/dcn31/dcn31_optc.c | 1 -
.../amd/display/dc/optc/dcn314/dcn314_optc.c | 1 -
.../amd/display/dc/optc/dcn32/dcn32_optc.c | 1 -
.../amd/display/dc/optc/dcn35/dcn35_optc.c | 1 -
.../amd/display/dc/optc/dcn401/dcn401_optc.c | 1 -
.../amd/display/dc/optc/dcn42/dcn42_optc.c | 1 -
20 files changed, 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index a416efcc9325..cfca7af6cd1f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -955,15 +955,6 @@ enum dc_status dcn30_setup_hdmi_frl_link(
return status;
}
-void dcn30_hw_set_vstartup_dsc_frl(struct dc *dc,
- struct pipe_ctx *pipe_ctx)
-{
- (void)dc;
- if (pipe_ctx->stream_res.tg->funcs->set_vstartup_dsc_frl)
- pipe_ctx->stream_res.tg->funcs->set_vstartup_dsc_frl(
- pipe_ctx->stream_res.tg);
-}
-
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
union dmub_rb_cmd cmd;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
index 2306354e90af..a963d360a368 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
@@ -85,9 +85,6 @@ int dcn30_hw_get_max_fva_factor(struct dc *dc,
struct dc_crtc_timing *timing,
unsigned int max_pixel_clock);
-void dcn30_hw_set_vstartup_dsc_frl(struct dc *dc,
- struct pipe_ctx *pipe_ctx);
-
bool dcn30_does_plane_fit_in_mall(struct dc *dc,
unsigned int pitch,
unsigned int height,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index cd151c75f59e..26c7386a8a36 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -106,7 +106,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.enable_dp_link_output = dce110_enable_dp_link_output,
.disable_link_output = dce110_disable_link_output,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
.get_dcc_en_bits = dcn10_get_dcc_en_bits,
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index 69b8e7030fa4..23b30d6f3956 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -99,7 +99,6 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.set_backlight_level = dcn21_set_backlight_level,
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
.set_pipe = dcn21_set_pipe,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 8c50604a4895..98771fc443c7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -101,7 +101,6 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.set_backlight_level = dcn21_set_backlight_level,
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
.set_pipe = dcn21_set_pipe,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index 203c4f7ecd2b..0b3e8512ebf1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -98,7 +98,6 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.get_max_dispclk_mhz = dcn32_get_max_dispclk_mhz,
.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
.does_plane_fit_in_mall = NULL,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index c0cefeff6e85..fc18d2207711 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -108,7 +108,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.set_backlight_level = dcn31_set_backlight_level,
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
.set_pipe = dcn21_set_pipe,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index a852a2345296..19ec5b4edfdc 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -101,7 +101,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.set_backlight_level = dcn31_set_backlight_level,
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
.set_pipe = dcn21_set_pipe,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index e1cc16aa207c..d24a352937b4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -85,7 +85,6 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations,
.does_plane_fit_in_mall = NULL,
.set_backlight_level = dcn31_set_backlight_level,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
index e54d814b3ea9..49c13611a518 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
@@ -86,7 +86,6 @@ static const struct hw_sequencer_funcs dcn42_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link,
- .set_vstartup_dsc_frl = dcn30_hw_set_vstartup_dsc_frl,
.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
.does_plane_fit_in_mall = NULL,
.set_backlight_level = dcn31_set_backlight_level,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 34e386e16d0c..2d74186844d4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -1437,9 +1437,6 @@ struct hw_sequencer_funcs {
unsigned int (*get_max_dispclk_mhz)(struct dc *dc,
struct dc_state *context);
- void (*set_vstartup_dsc_frl)(struct dc *dc,
- struct pipe_ctx *pipe_ctx);
-
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index cf124838f354..8f72322aab4b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -498,7 +498,6 @@ struct timing_generator_funcs {
int (*get_max_hw_supported_fva_factor)(struct timing_generator *optc,
struct dc_crtc_timing *timing,
unsigned int max_pixclk_100hz);
- void (*set_vstartup_dsc_frl)(struct timing_generator *optc);
void (*set_vtotal_change_limit)(struct timing_generator *optc,
uint32_t limit);
void (*align_vblanks)(struct timing_generator *master_optc,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
index 78fd8d262de3..90ec4cb8a9dd 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
@@ -320,27 +320,6 @@ bool optc3_get_pipe_update_pending(struct timing_generator
*optc)
return (flip_pending == 1 || dc_update_pending == 1);
}
-void optc3_set_vstartup_dsc_frl(struct timing_generator *optc)
-{
- struct optc *optc1 = DCN10TG_FROM_TG(optc);
- unsigned int vblank_end = 0;
- unsigned int vstartup_start = 0;
-
- REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_END, &vblank_end);
- REG_GET(OTG_VSTARTUP_PARAM, VSTARTUP_START, &vstartup_start);
-
- /* In FRL+DSC mode the VSYNC is generated in OTG at start of HBALNK
- * before frame start (VCOUNT=0 and HCOUNT=0). We need to program
- * VSTARTUP at least one line before frame start to ensure the VSYNC
- * will be generated in VRR mode. We need to program
- * VSTARTUP_START >= V_BLANK_END + 1.
- * When fullscreen = false,
- * global_sync will restore VSTARTUP_START to normal value
- */
- if (vblank_end >= vstartup_start)
- REG_SET(OTG_VSTARTUP_PARAM, 0, VSTARTUP_START,
- vblank_end+1);
-}
/**
* optc3_set_timing_double_buffer() - DRR double buffering control
*
@@ -436,7 +415,6 @@ static const struct timing_generator_funcs dcn30_tg_funcs =
{
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc3_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
index 8a88867f4361..16c5610b49ac 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
@@ -349,7 +349,6 @@ void optc3_triplebuffer_lock(struct timing_generator *optc);
void optc3_program_blank_color(struct timing_generator *optc,
const struct tg_color *blank_color);
-void optc3_set_vstartup_dsc_frl(struct timing_generator *optc);
void optc3_set_vtotal_change_limit(struct timing_generator *optc,
uint32_t limit);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
index bbf703777f72..98aaa22ce81c 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
@@ -500,7 +500,6 @@ static const struct timing_generator_funcs dcn31_tg_funcs =
{
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc3_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
index 4d4b517575e2..a7cf34937b2f 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
@@ -244,7 +244,6 @@ static const struct timing_generator_funcs dcn314_tg_funcs
= {
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc3_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index 99258b2fb14e..60e546b69a05 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -354,7 +354,6 @@ static const struct timing_generator_funcs dcn32_tg_funcs =
{
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc3_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index f6183c2e78e4..a880e4a6d165 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -595,7 +595,6 @@ static const struct timing_generator_funcs dcn35_tg_funcs =
{
.set_h_timing_div_manual_mode =
optc32_set_h_timing_div_manual_mode,
.set_out_mux = optc3_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index 581517c9cec4..a6d76f451cf8 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -521,7 +521,6 @@ static const struct timing_generator_funcs dcn401_tg_funcs
= {
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc401_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
index f5280bc3c7ec..ed66a2bbb8ae 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
@@ -250,7 +250,6 @@ static struct timing_generator_funcs dcn42_tg_funcs = {
.wait_otg_disable = optc35_wait_otg_disable,
.set_out_mux = optc401_set_out_mux,
.set_drr_trigger_window = optc3_set_drr_trigger_window,
- .set_vstartup_dsc_frl = optc3_set_vstartup_dsc_frl,
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
--
2.54.0
