AMD General Hi Timur,
Thanks for clarifying. yes, please push the Navi 48 WIP branch when you have a chance, useful to compare side-by-side. Patch 5 / WDOORBELL on ih_v7_0: I have been able to confirm that doorbell ACK does not free the CAM slot on the NV4 family (gfx1200/1201). I verified empirically, slots walk monotonically until the CAM fills, then HW silently drops retry events. MMIO write to regIH_RETRY_CAM_ACK does free it. Almost certainly required for your Navi 48 attempt. Why PTE update doesn't reach UTC L0: Most likely a race between the SDMA PTE-update job completing and the CAM ACK firing the IRQ for re-handling. Until SDMA finishes the write + invalidation propagates, UTC L0 keeps getting the stale "invalid" reply which is exactly your symptom. To inspect with umr: clone https://gitlab.freedesktop.org/tomstdenis/umr and use scripts/diag/dump_all_cpc_info.sh (needs halt_if_hws_hang=1 gpu_recovery=0). For UTC specifically: umr -i <gpu> -O bits -r '*.*.regGCVM_L2_STATUS' (look at L2_BUSY and CONTEXT_DOMAIN_BUSY per-VMID bits) and regGCVM_L2_PROTECTION_FAULT_STATUS (empty + busy = translation timeout, not denial). Page-table walk to confirm PTE landed: sudo umr -i <gpu> -vm <vmid>@<va> 1. Your ACK-after-SDMA-fence idea: good catch. We hadn't dug into that race because the BO-clear deadlock dominates on NV4, but the ordering bug is almost certainly there too. Fence callback is the right shape, cleaner than blocking the worker. Would be a generic fix benefiting both Navi 3 and 4. Happy to review if you take a swing. IH1 routing: fair point. I just inherited the existing IH0 path and haven't tried IH1. On the list once CAM ACK and fence ordering are stable. AMIR SHETAIA Senior Software Development Engineer | AMD Software Platform Architecture Team ---------------------------------------------------------------------------------------------------------------------------------- 1 Commerce Valley Drive, Markham, ON L3T 7X6 LinkedIn | Instagram | X | amd.com -----Original Message----- From: Timur Kristóf <[email protected]> Sent: Wednesday, May 13, 2026 6:12 PM To: Alex Deucher <[email protected]>; Shetaia, Amir <[email protected]> Cc: [email protected]; Deucher, Alexander <[email protected]>; Koenig, Christian <[email protected]>; Marek Olšák <[email protected]>; Natalie Vock <[email protected]>; Melissa Wen <[email protected]> Subject: Re: [PATCH 0/6] drm/amdgpu: Improve retry fault handling Hi Amir, > Timur, you are right, I see your patch 6 already does the MMIO ACK for > gmc_v11_0/ih_v6_0. I missed that. The gap is only in patch 5's ih_v7_0 > implementation, which still does WDOORBELL. that's where I'd suggest > swapping in MMIO for NV4. First, let me clear up a slight misunderstanding here. The patch series that I sent here only contains what I managed to get working on Navi 31, it does not contain any code from my attempt at Navi 48. The patch 5 is just a slight refactor of the pre-existing code and (intentionally) doesn't contain any functional changes. It seems that IH 7.1 relies on the doorbell, so I didn't want to remove it, albeit I have no means to verify if that actually works or not. If you like, I can push a few WIP patches to a different branch tomorrow to show you exactly what I did on Navi 48. However, I wouldn't want to submit that to the mailing list without first making sure that it works well. > 1. "Fault never resolves on NV48" different shape from our > broken-CAM-ACK symptom. > You're right, those are different. Our cam-walk-monotonically symptom > only shows up when CAM is enabled but the ACK is broken. > On your NV48 setup CAM > probably isn't enabled at all (your patch 6 only enables it for > ih_v6_0_irq_init, no equivalent in ih_v7_0_irq_init) For the attempt on Navi 48, I enabled the CAM in ih_v7_0 the same way I do for ih_v6_0 in the series. But, because I couldn't get it fully working, I didn't include any of that code in the series. > so retries fire > repeatedly on the IH ring instead of being deduped by CAM. That > matches what you're seeing .. amdgpu_vm_handle_fault keeps being > called but each call is on a fresh IRQ for the same address. > Two things that could be happening underneath: > - The fault handler runs but the updated PTE never reaches UTC L0 (TLB > invalidation gap). On NV4 we see this as "valid PTEs failing to translate" > in our UMR captures. I think this explanation may fit what I saw. Why is it not reaching UTC L0? Also, how do you inspect this stuff in umr? > 2. What bits we check on src_data[2]: > > Honestly, we don't use src_data[2] for retry detection. We use it only for > the cam_index: cam_index = entry->src_data[2] & 0x3ff; /* low 10 bits = > CAM slot */ > For retry detection we initially used the gfx9 constant on src_data[1] > like you, but observed the bit cleared on a lot of NV4 events that > should have been retries (waves were hung in xnack-stall but no IH event > matched). > So > we just go through the retry path unconditionally on NV4 I see. I think I needed to change some gfxhub registers to get those src_data bits that you are missing. > and let > amdgpu_vm_handle_fault sort it out via SVM range migration. May be > specific to gfx1201 / our test path My test case is a simple Vulkan shader which I am executing with vkrunner. Each shader invocation does an out of bounds read from a different page. For Navi 31 (and Strix Halo), I started out with just 1 page fault, and once I could mitigate that reliably, I turned it up to several hundred faults. > 3. TLB flush making it worse .. clue about what to do: > > Honest answer: not really, not a SW-only fix. Our 1 GiB hang is an > architectural deadlock ... ih_soft_work blocks on a dma_fence for an > SDMA BO-clear, the BO-clear is stalled on a GCR (cache flush) request, > and the GC cache block isn't ACK'ing the GCR while UTC L2 is saturated > by the user shader's XNACK retry storm. Adding a TLB flush adds > another translation request to the same saturated UTC, which is why it > makes things worse. This may be related to a flaw in amdgpu_gmc_handle_retry_fault(): what the function does is first call amdgpu_vm_handle_fault() which kicks off an SDMA job to update page tables, and then it ACKs the filter CAM. However, at the moment when the CAM is ACKed, the SDMA job is not finished yet, so the CP sees that the page is still invalid and the page fault interrupt is fired again. I actually noticed that on Navi 31 too, but it's just not fatal there. It just basically handles the same page fault twice. Once we solve this flaw, I would like to propose to enable retry faults by default on Navi 3. Here is an idea for a solution: Instead of ACKing the CAM right away, we should do it after the SDMA fence is signalled, ie. when we are sure the page tables are updated. Maybe we can set a callback on the fence and do it there, though it would require a slight code churn to get that to work. What do you think? > 4. IH1 ring on NV4: > > Same as you ... retry faults on NV4 always come in on IH0. We delegate > from > IH0 to ih.ring_soft (amdgpu_irq_delegate(adev, entry, 8)) so the > SVM/migration path can sleep, but the original entry is on IH0. We > haven't tried IH1 routing. Why, though? The ih_v7_0 code does set up the IH1 ring and configure it exactly the same as the ih_v6_0, so I don't see why it wouldn't work? > Re your branch: thanks for the gitlab link, easier than digging > through patchwork. > I'll cherry-pick patches 1, 3, 4 into our test build to see if patch 4 > cleans up the timestamp filter delta we're seeing (97k entered / 2.8k > completed at 1 GiB might be partly explained by your Strix Halo bug). The timestamp issue actually gave me an endless headache when I first got into this topic in December. I hope the patch helps! Best regards, Timur
