On 5/13/26 18:30, Timur Kristóf wrote: > When the fault stop mode isn't AMDGPU_VM_FAULT_STOP_ALWAYS, > these bits should be programmed to 0. > > Program CRASH_ON_NO_RETRY_FAULT and CRASH_ON_RETRY_FAULT > always, to make sure to clear the bits when we don't want > to crash. > > Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Christian König <[email protected]> Can you re-order the patches to put the already reviewed ones first? I have a bit of doubts if if patch #2 is correct, but that one here is clearly a bug fix which we should merge ASAP. Thanks, Christian. > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 14 ++++++-------- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 10 ++++------ > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 10 ++++------ > 9 files changed, 38 insertions(+), 56 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > index 8fdf66ad265c..3c6c20e529a9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > @@ -449,12 +449,10 @@ static void > gfxhub_v11_5_0_set_fault_enable_default(struct amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > index 84344c67013a..9234a66a439a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > @@ -454,12 +454,10 @@ static void > gfxhub_v12_0_set_fault_enable_default(struct amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > index e505aaf8b447..82ee96b5ef4b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > @@ -633,19 +633,17 @@ static void > gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev > tmp = REG_SET_FIELD(tmp, > GCVM_L2_PROTECTION_FAULT_CNTL_LO32, > OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT, > value); > - if (!value) > - tmp = REG_SET_FIELD(tmp, > - GCVM_L2_PROTECTION_FAULT_CNTL_LO32, > - CRASH_ON_NO_RETRY_FAULT, 1); > + tmp = REG_SET_FIELD(tmp, > + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, > + CRASH_ON_NO_RETRY_FAULT, !value); > WREG32_SOC15(GC, GET_INST(GC, i), > regGCVM_L2_PROTECTION_FAULT_CNTL_LO32, tmp); > > tmp = RREG32_SOC15(GC, GET_INST(GC, i), > regGCVM_L2_PROTECTION_FAULT_CNTL_HI32); > - if (!value) > - tmp = REG_SET_FIELD(tmp, > - GCVM_L2_PROTECTION_FAULT_CNTL_HI32, > - CRASH_ON_RETRY_FAULT, 1); > + tmp = REG_SET_FIELD(tmp, > + GCVM_L2_PROTECTION_FAULT_CNTL_HI32, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, GET_INST(GC, i), > regGCVM_L2_PROTECTION_FAULT_CNTL_HI32, tmp); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index c8a615147904..2b20b86236be 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -403,12 +403,10 @@ static void gfxhub_v1_0_set_fault_enable_default(struct > amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > index afc8c6a6f1bb..182cf3994512 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > @@ -516,12 +516,10 @@ static void > gfxhub_v1_2_xcc_set_fault_enable_default(struct amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, GET_INST(GC, i), > regVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, GET_INST(GC, i), > regVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > index a27bb37b2a11..35ef43137f1d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > @@ -418,12 +418,10 @@ static void gfxhub_v2_0_set_fault_enable_default(struct > amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > index db56f7a61d61..c6b610c48540 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > @@ -449,12 +449,10 @@ static void gfxhub_v2_1_set_fault_enable_default(struct > amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > index 97585c7b879c..0d8b8980898e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > @@ -446,12 +446,10 @@ static void gfxhub_v3_0_set_fault_enable_default(struct > amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > index 72f24372a4e8..766dc0ce738b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > @@ -434,12 +434,10 @@ static void > gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev, > WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); > - if (!value) { > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_NO_RETRY_FAULT, 1); > - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > - CRASH_ON_RETRY_FAULT, 1); > - } > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_NO_RETRY_FAULT, !value); > + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, > + CRASH_ON_RETRY_FAULT, !value); > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); > > tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2);
