On 5/19/26 10:22, Timur Kristóf wrote:
> These UVD versions don't fully support GPUVM and are only
> validated to work when their VCPU BO is placed in VRAM.
> 
> Signed-off-by: Timur Kristóf <[email protected]>

Reviewed-by: Christian König <[email protected]>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index 3a3bc0d370fa..1e59ca924abe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -188,6 +188,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>       const struct common_firmware_header *hdr;
>       unsigned int family_id;
>       int i, j, r;
> +     u32 vcpu_bo_domain;
>  
>       INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
>  
> @@ -319,12 +320,20 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
>               bo_size += 
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>  
> +     /* UVD 5.0 and newer HW can use 64 bit addressing. */
> +     adev->uvd.address_64_bit =
> +             !amdgpu_device_ip_block_version_cmp(adev, 
> AMD_IP_BLOCK_TYPE_UVD, 5, 0);
> +
> +     vcpu_bo_domain = AMDGPU_GEM_DOMAIN_VRAM;
> +     if (adev->uvd.address_64_bit)
> +             vcpu_bo_domain |= AMDGPU_GEM_DOMAIN_GTT;
> +
>       for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
>               if (adev->uvd.harvest_config & (1 << j))
>                       continue;
> +
>               r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
> -                                         AMDGPU_GEM_DOMAIN_VRAM |
> -                                         AMDGPU_GEM_DOMAIN_GTT,
> +                                         vcpu_bo_domain,
>                                           &adev->uvd.inst[j].vcpu_bo,
>                                           &adev->uvd.inst[j].gpu_addr,
>                                           &adev->uvd.inst[j].cpu_addr);
> @@ -339,10 +348,6 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>               adev->uvd.filp[i] = NULL;
>       }
>  
> -     /* from uvd v5.0 HW addressing capacity increased to 64 bits */
> -     if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 
> 0))
> -             adev->uvd.address_64_bit = true;
> -
>       r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
>       if (r)
>               return r;

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