On Wed, May 20, 2026 at 4:29 AM Jeevana Muthyala <[email protected]> wrote:
>
> From: Jeevana Muthyala <[email protected]>
>
> Signed-off-by: Jeevana Muthyala <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 40 ++++++++++++++++++++++++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index d5f49fa33bee..4223159c9a3b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1234,6 +1234,38 @@ static const struct amdgpu_ring_funcs
> vcn_v5_0_0_unified_ring_vm_funcs = {
> .reset = vcn_v5_0_0_ring_reset,
> };
>
> +static const struct amdgpu_ring_funcs
> vcn_v5_0_0_unified_ring_vm_funcs_secure = {
> + .type = AMDGPU_RING_TYPE_VCN_ENC,
> + .align_mask = 0x3f,
> + .nop = VCN_ENC_CMD_NO_OP,
> + .secure_submission_supported = true,
> + .no_user_fence = true,
> + .get_rptr = vcn_v5_0_0_unified_ring_get_rptr,
> + .get_wptr = vcn_v5_0_0_unified_ring_get_wptr,
> + .set_wptr = vcn_v5_0_0_unified_ring_set_wptr,
> + .emit_frame_size =
> + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
> + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
> + 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
> + 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
> + 1, /* vcn_v2_0_enc_ring_insert_end */
> + .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
> + .emit_ib = vcn_v2_0_enc_ring_emit_ib,
> + .emit_fence = vcn_v2_0_enc_ring_emit_fence,
> + .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
> + .test_ring = amdgpu_vcn_enc_ring_test_ring,
> + .test_ib = amdgpu_vcn_unified_ring_test_ib,
> + .insert_nop = amdgpu_ring_insert_nop,
> + .insert_end = vcn_v2_0_enc_ring_insert_end,
> + .pad_ib = amdgpu_ring_generic_pad_ib,
> + .begin_use = amdgpu_vcn_ring_begin_use,
> + .end_use = amdgpu_vcn_ring_end_use,
> + .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
> + .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
> + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
> + .reset = vcn_v5_0_0_ring_reset,
> +};
> +
> /**
> * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions
> *
> @@ -1244,12 +1276,18 @@ static const struct amdgpu_ring_funcs
> vcn_v5_0_0_unified_ring_vm_funcs = {
> static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
> + const struct amdgpu_ring_funcs *funcs;
> +
> + if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 3, 0))
> + funcs = &vcn_v5_0_0_unified_ring_vm_funcs_secure;
> + else
> + funcs = &vcn_v5_0_0_unified_ring_vm_funcs;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
>
> - adev->vcn.inst[i].ring_enc[0].funcs =
> &vcn_v5_0_0_unified_ring_vm_funcs;
> + adev->vcn.inst[i].ring_enc[0].funcs = funcs;
This could be simplified to just:
if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 3, 0))
adev->vcn.inst[i].ring_enc[0].funcs =
&vcn_v5_0_0_unified_ring_vm_funcs_secure;
else
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs;
With that fixed,
Reviewed-by: Alex Deucher <[email protected]>
> adev->vcn.inst[i].ring_enc[0].me = i;
> }
> }
> --
> 2.43.0
>
