[PATCH] drm/amdgpu/vcn_v4_0.c: enable secure submission on unified ring

[Jeevana Muthyala]

Signed-off-by: Jeevana Muthyala <jmuth...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 43 +++++++++++++++++++++++----
 1 file changed, 38 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index ff7269bafae8..bc623e3eb68d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1992,7 +1992,7 @@ static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring,
        return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 }
 
-static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
+static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_ENC,
        .align_mask = 0x3f,
        .nop = VCN_ENC_CMD_NO_OP,
@@ -2025,6 +2025,40 @@ static struct amdgpu_ring_funcs 
vcn_v4_0_unified_ring_vm_funcs = {
        .reset = vcn_v4_0_ring_reset,
 };
 
+static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs_secure = {
+       .type = AMDGPU_RING_TYPE_VCN_ENC,
+       .align_mask = 0x3f,
+       .nop = VCN_ENC_CMD_NO_OP,
+       .secure_submission_supported = true,
+       .no_user_fence = true,
+       .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata),
+       .get_rptr = vcn_v4_0_unified_ring_get_rptr,
+       .get_wptr = vcn_v4_0_unified_ring_get_wptr,
+       .set_wptr = vcn_v4_0_unified_ring_set_wptr,
+       .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
+       .emit_frame_size =
+               SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+               SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+               4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
+               5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
+               1, /* vcn_v2_0_enc_ring_insert_end */
+       .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
+       .emit_ib = vcn_v2_0_enc_ring_emit_ib,
+       .emit_fence = vcn_v2_0_enc_ring_emit_fence,
+       .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
+       .test_ring = amdgpu_vcn_enc_ring_test_ring,
+       .test_ib = amdgpu_vcn_unified_ring_test_ib,
+       .insert_nop = amdgpu_ring_insert_nop,
+       .insert_end = vcn_v2_0_enc_ring_insert_end,
+       .pad_ib = amdgpu_ring_generic_pad_ib,
+       .begin_use = amdgpu_vcn_ring_begin_use,
+       .end_use = amdgpu_vcn_ring_end_use,
+       .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
+       .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
+       .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+       .reset = vcn_v4_0_ring_reset,
+};
+
 /**
  * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
  *
@@ -2041,10 +2075,9 @@ static void vcn_v4_0_set_unified_ring_funcs(struct 
amdgpu_device *adev)
                        continue;
 
                if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
-                       
vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
-
-               adev->vcn.inst[i].ring_enc[0].funcs =
-                      (const struct amdgpu_ring_funcs 
*)&vcn_v4_0_unified_ring_vm_funcs;
+                  adev->vcn.inst[i].ring_enc[0].funcs = (const struct 
amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs_secure;
+               else
+                  adev->vcn.inst[i].ring_enc[0].funcs = (const struct 
amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
                adev->vcn.inst[i].ring_enc[0].me = i;
        }
 }
-- 
2.43.0