Applied.  Thanks!

Alex

On Wed, May 27, 2026 at 10:34 AM Timur Kristóf <[email protected]> wrote:
>
> On 2026. május 27., szerda 15:19:31 közép-európai nyári idő Donet Tom wrote:
> > When mapping VRAM pages into the GART page table,
> > amdgpu_gart_map_vram_range() assumes that the system page size is the
> > same as the GPU page size.
> >
> > On systems with non-4K page sizes, multiple GPU pages can exist within
> > a single CPU page. As a result, the mappings are created incorrectly
> > because fewer page table entries are programmed than required.
> >
> > Fix this by programming the mappings correctly for non-4K page size
> > systems.
> >
> > Fixes: 237d623ae659 ("drm/amdgpu/gart: Add helper to bind VRAM pages (v2)")
> > Reviewed-by: Christian König <[email protected]>
> > Signed-off-by: Donet Tom <[email protected]>
> > ---
>
> Thank you! The fix looks good to me.
> Reviewed-by: Timur Kristóf <[email protected]>
>
>
> > v2 -> v3
> > - Addressed Christian's review comments and added the Reviewed-by tag.
> >
> > v2 -
> > https://lore.kernel.org/all/[email protected]
> > / v1 -
> > https://lore.kernel.org/all/[email protected]
> > / ---
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index b6f849d51c2e..c4c21dbbbdbf
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> > @@ -394,7 +394,8 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device
> > *adev, uint64_t pa, uint64_t start_page, uint64_t num_pages,
> >                               uint64_t flags, void *dst)
> >  {
> > -     u32 i, idx;
> > +     u32 i, j, t, idx;
> > +     u64 page_base;
> >
> >       /* The SYSTEM flag indicates the pages aren't in VRAM. */
> >       WARN_ON_ONCE(flags & AMDGPU_PTE_SYSTEM);
> > @@ -402,9 +403,12 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device
> > *adev, uint64_t pa, if (!drm_dev_enter(adev_to_drm(adev), &idx))
> >               return;
> >
> > -     for (i = 0; i < num_pages; ++i) {
> > -             amdgpu_gmc_set_pte_pde(adev, dst,
> > -                     start_page + i, pa + AMDGPU_GPU_PAGE_SIZE *
> i, flags);
> > +     page_base = pa;
> > +     for (i = 0, t = 0; i < num_pages; i++) {
> > +             for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++)
> {
> > +                     amdgpu_gmc_set_pte_pde(adev, dst, start_page
> + t, page_base, flags);
> > +                     page_base += AMDGPU_GPU_PAGE_SIZE;
> > +             }
> >       }
> >
> >       drm_dev_exit(idx);
>
>
>
>

Reply via email to