AMD General Hi Thomas,
As currently structured, every path in the switch statement-including the default case-already returns explicitly. This means the end of the function is unreachable, and introducing a trailing return could result in dead code. In fact, adding such a return might trigger "unreachable code" warnings from compilers or static analyzers like Smatch or Coverity. Best regards, Stanley > -----Original Message----- > From: Chai, Thomas <[email protected]> > Sent: Wednesday, May 27, 2026 6:44 PM > To: Yang, Stanley <[email protected]>; [email protected] > Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao > <[email protected]>; Li, Candice <[email protected]> > Subject: RE: [PATCH 1/2] drm/amd/ras: Return RAS TA injection result to > userspace > > AMD General > > The __check_ras_ta_cmd_resp function should have a return statement added > at the end. > > Fixed that the series is: > > Reviewed-by: YiPeng Chai <[email protected]> > > > Best Regards, > Thomas > -----Original Message----- > From: Yang, Stanley <[email protected]> > Sent: Tuesday, May 26, 2026 2:06 PM > To: [email protected] > Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao > <[email protected]>; Chai, Thomas <[email protected]>; Li, Candice > <[email protected]>; Yang, Stanley <[email protected]> > Subject: [PATCH 1/2] drm/amd/ras: Return RAS TA injection result to > userspace > > Return RAS TA injection result to userspace that avoid app continue to load > work once injection failed. > > Changed from V1: > refactor function __check_ras_ta_cmd_resp return > ras ta corresponding error. > return res instead of RAS_CMD__SUCCESS in function > amdgpu_ras_submit_cmd. > > Signed-off-by: Stanley.Yang <[email protected]> > --- > .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c | 2 +- > drivers/gpu/drm/amd/ras/rascore/ras_psp.c | 21 ++++++++++--------- > 2 files changed, 12 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c > b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c > index c22e53e84207..ff7f9af980d5 100644 > --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c > +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c > @@ -288,5 +288,5 @@ int amdgpu_ras_submit_cmd(struct > ras_core_context *ras_core, struct ras_cmd_ctx > return RAS_CMD__SUCCESS_EXEED_BUFFER; > } > > - return RAS_CMD__SUCCESS; > + return res; > } > diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c > b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c > index 5d556e2a7000..358f602b167d 100644 > --- a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c > +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c > @@ -317,36 +317,37 @@ static int send_psp_cmd(struct ras_core_context > *ras_core, > return ret; > } > > -static void __check_ras_ta_cmd_resp(struct ras_core_context *ras_core, > +static int __check_ras_ta_cmd_resp(struct ras_core_context *ras_core, > struct ras_ta_cmd *ras_cmd) { > - > if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { > RAS_DEV_WARN(ras_core->dev, "ECC switch disabled\n"); > ras_cmd->ras_status = > RAS_TA_STATUS__ERROR_RAS_NOT_AVAILABLE; > - } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) > + } else if > + (ras_cmd->ras_out_message.flags.reg_access_failure_flag) { > RAS_DEV_WARN(ras_core->dev, "RAS internal register access > blocked\n"); > + ras_cmd->ras_status = > RAS_TA_STATUS__TEE_ERROR_ACCESS_DENIED; > + } > > switch (ras_cmd->ras_status) { > + case RAS_TA_STATUS__SUCCESS: > + return 0; > case RAS_TA_STATUS__ERROR_UNSUPPORTED_IP: > RAS_DEV_WARN(ras_core->dev, > "RAS WARNING: cmd failed due to unsupported ip\n"); > - break; > + return -EINVAL; > case RAS_TA_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: > RAS_DEV_WARN(ras_core->dev, > "RAS WARNING: cmd failed due to unsupported error > injection\n"); > - break; > - case RAS_TA_STATUS__SUCCESS: > - break; > + return -EINVAL; > case RAS_TA_STATUS__TEE_ERROR_ACCESS_DENIED: > if (ras_cmd->cmd_id == RAS_TA_CMD_ID__TRIGGER_ERROR) > RAS_DEV_WARN(ras_core->dev, > "RAS WARNING: Inject error to critical > region is not > allowed\n"); > - break; > + return -EACCES; > default: > RAS_DEV_WARN(ras_core->dev, > "RAS WARNING: ras status = 0x%X\n", > ras_cmd->ras_status); > - break; > + return -EINVAL; > } > } > > @@ -417,7 +418,7 @@ static int send_ras_ta_runtime_cmd(struct > ras_core_context *ras_core, > if (!ras_cmd->ras_status && out && out_size) > memcpy(out, &ras_cmd->ras_out_message, out_size); > > - __check_ras_ta_cmd_resp(ras_core, ras_cmd); > + ret = __check_ras_ta_cmd_resp(ras_core, ras_cmd); > > unlock: > mutex_unlock(&ta_ctx->ta_mutex); > -- > 2.43.0 >
