From: Alex Deucher <[email protected]> Separate settings for gfx (ME) and compute (MEC). Use this rather than explicitly specifying it.
Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Jesse Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 7 +++++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 7 +++++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 2a548b22725f..22fb90e229dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -116,6 +116,7 @@ struct amdgpu_mec { u32 num_pipe_per_mec; u32 num_queue_per_pipe; void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; + bool use_mmio_for_reset; }; struct amdgpu_mec_bitmap { @@ -401,6 +402,7 @@ struct amdgpu_me { uint32_t num_pipe_per_me; uint32_t num_queue_per_pipe; void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; + bool use_mmio_for_reset; /* These are the resources for which amdgpu takes ownership */ DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 455fe4b3c205..50d3990a00c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1905,6 +1905,9 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + adev->gfx.me.use_mmio_for_reset = false; + adev->gfx.mec.use_mmio_for_reset = true; + return 0; } @@ -6780,7 +6783,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; - bool use_mmio = false; + bool use_mmio = adev->gfx.me.use_mmio_for_reset; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); @@ -6811,7 +6814,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; - bool use_mmio = true; + bool use_mmio = adev->gfx.mec.use_mmio_for_reset; int r = 0; amdgpu_ring_reset_helper_begin(ring, timedout_fence); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 3c6f234cfb29..03b1fcc04655 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -1603,6 +1603,9 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + adev->gfx.me.use_mmio_for_reset = false; + adev->gfx.mec.use_mmio_for_reset = true; + return 0; } @@ -5216,7 +5219,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; - bool use_mmio = false; + bool use_mmio = adev->gfx.me.use_mmio_for_reset; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); @@ -5247,7 +5250,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; - bool use_mmio = true; + bool use_mmio = adev->gfx.mec.use_mmio_for_reset; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); -- 2.49.0
